SST49LF004B-33-4C-NH Microchip Technology, SST49LF004B-33-4C-NH Datasheet - Page 12

• Manufacturer Part Number: SST49LF004B-33-4C-NH
• Description: Flash 512K X 8 33ns
• Manufacturer: Microchip Technology

Specifications of SST49LF004B-33-4C-NH

• Data Bus Width: 8 bit
• Memory Type: NAND
• Memory Size: 4 Mbit
• Architecture: Sectored
• Interface Type: LPC
• Access Time: 33 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-32
• Organization: 512 KB x 8
• Lead Free Status / Rohs Status: No

EOL Data Sheet
Firmware Memory Read Cycle
TABLE 4: F
©2007 Silicon Storage Technology, Inc.
FIGURE 4: F
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
3-9
LFRAME#
10
11
12
13
14
15
16
17
1
2
LAD[3:0]
LCLK
IRMWARE
MADDR
RSYNC
START
MSIZE
IDSEL
Name
TAR0
TAR1
TAR0
TAR1
Field
DATA
DATA
IRMWARE
M
EMORY
1101b
Start
M
Field Contents
0000 (READY)
EMORY
0000 (1 Byte)
0000 to 1111
1111 (float)
1111 (float)
LAD[3:0]
IDSEL
0000b
YYYY
ZZZZ
ZZZZ
R
1101
1111
1111
EAD
A[27:24]
R
EAD
C
1
YCLE
A[23:20] A[19:16]
C
YCLE
F
IN then Float
Float then IN
Float then
IELD
Direction
OUT then
LAD[3:0]
W
OUT
OUT
OUT
OUT
Float
A[15:12]
MADDR
IN
IN
IN
IN
AVEFORM
D
EFINITIONS
A[11:8]
12
In this clock cycle, the master has driven the bus to all ‘1’s
Comments
LFRAME# must be active (low) for the device to respond.
Only the last field latched before LFRAME# transitions high
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
Indicates which
IDSEL (ID select) field matches the value of ID[3:0], the device
will respond to the LPC bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
The MSIZE field indicates how many bytes will be trans-
ferred during multi-byte operations. The
only supports single-byte operation. MSIZE=0000b
and then floats the bus, prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
The
cycle.
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data.
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
The host resumes control of the bus during this cycle.
A[7:4]
SST49LF004B
A[3:0]
MSIZE
0000b
SST49LF004B
TAR0
1111b
takes control of the bus during this
Tri-State
TAR1
SST49LF004B
RSYNC
4 Mbit Firmware Hub
0000b
device should respond. If the
D[3:0]
DATA
SST49LF004B
drives the bus to all
D[7:4]
SST49LF004B
S71307-03-EOL
1307 F03.0
TAR
T4.1 1307
12/07