SST49LF004B-33-4C-NH Microchip Technology, SST49LF004B-33-4C-NH Datasheet - Page 18

• Manufacturer Part Number: SST49LF004B-33-4C-NH
• Description: Flash 512K X 8 33ns
• Manufacturer: Microchip Technology

Specifications of SST49LF004B-33-4C-NH

• Data Bus Width: 8 bit
• Memory Type: NAND
• Memory Size: 4 Mbit
• Architecture: Sectored
• Interface Type: LPC
• Access Time: 33 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-32
• Organization: 512 KB x 8
• Lead Free Status / Rohs Status: No

EOL Data Sheet
TABLE 9: O
Data# Polling DQ
When the SST49LF004B device is in the internal Program
operation, any attempt to read DQ
plement of the true data. Once the Program operation is
completed, DQ
though DQ
completion of an internal Write operation, the remaining
data outputs may still be invalid. Valid data will appear on
the entire data bus in subsequent successive Read cycles
after an interval of 1 µs. During an internal Erase operation,
any attempt to read DQ
nal Erase operation is completed, DQ
Data# Polling is valid after the rising edge of the fourth WE#
pulse for the Program operation. For Sector-Erase, Block-
Erase, or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of the sixth WE# pulse. See Figure 13 for Data#
Polling timing diagram. Proper status will not be given using
Data# Polling if the address is in the invalid range.
Toggle Bit DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and '1's, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of the fourth WE#
pulse for Program operation. For Sector-Erase, Block-
Erase or Chip-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# pulse. See Figure 14 for Toggle Bit
timing diagram.
©2007 Silicon Storage Technology, Inc.
Mode
Read
Program
Erase
Reset
Write Inhibit
Product Identification
1. X can be V
2. Device ID = 60H for SST49LF004B
7
may have valid data immediately following the
PERATION
IL
7
6
or V
will produce true data. Note that even
7
IH
, but no other value.
7
will produce a '0'. Once the inter-
M
ODES
6
RST#
V
V
V
V
V
V
will produce alternating '0's
IH
IH
IH
IH
IH
IL
S
7
ELECTION
will produce the com-
7
will produce a '1'.
OE#
V
V
V
V
V
X
IH
IH
IL
IL
IL
(PP M
ODE
)
WE#
V
V
V
V
V
X
18
IH
IH
IH
IL
IL
Data Protection (PP Mode)
The SST49LF004B device provides both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit
the Write operation. This prevents inadvertent writes during
power-up or power-down.
Software Data Protection (SDP)
The SST49LF004B provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tion, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three-byte sequence.
The three-byte load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inadvert-
ent Write operations, e.g., during the system power-up or
power down. Any Erase operation requires the inclusion of
a five-byte load sequence.
DD
DQ
D
D
X
High Z
High Z/D
Manufacturer’s ID (BFH)
Device ID
Power Up/Down Detection: The Write operation is
1
OUT
IN
OUT
2
DD
is less than 1.5V.
4 Mbit Firmware Hub
Address
A
A
Sector or Block address,
XXH for Chip-Erase
X
X
A
A
IN
IN
18
18
- A
- A
SST49LF004B
1
1
= V
= V
S71307-03-EOL
IL
IL
, A
, A
0
0
= V
= V
T9.0 1307
IL
IH
12/07