74LV132PW NXP Semiconductors, 74LV132PW Datasheet - Page 3
![Gates (AND / NAND / OR / NOR) QUAD 2-INPUT NAND SCHMITT TRIG](/photos/15/59/155966/soic14_sml.jpg)
74LV132PW
Manufacturer Part Number
74LV132PW
Description
Gates (AND / NAND / OR / NOR) QUAD 2-INPUT NAND SCHMITT TRIG
Manufacturer
NXP Semiconductors
Datasheet
1.74LV132N112.pdf
(17 pages)
Specifications of 74LV132PW
Product
NAND
Logic Family
LV
Number Of Gates
4
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 12 mA
Low Level Output Current
12 mA
Propagation Delay Time
65 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-402
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Details
Other names
74LV132PW,112
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LV132PW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
74LV132PWЈ¬118
Manufacturer:
NXP
Quantity:
2 500
NXP Semiconductors
6. Pinning information
Table 2.
74LV132_5
Product data sheet
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
CC
Pin description
GND
1A
1B
1Y
2A
2B
2Y
6.1 Pinning
6.2 Pin description
1
2
3
4
5
6
7
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
132
001aac203
14
13
12
11
10
9
8
V
4B
4A
4Y
3B
3A
3Y
CC
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
Rev. 05 — 2 July 2009
Fig 5. Pin configuration DHVQFN14
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It cannot be
used as a supply pin or input.
index area
terminal 1
1B
1Y
2A
2B
2Y
Quad 2-input NAND Schmitt trigger
Transparent top view
2
3
4
5
6
74LV132
V
CC
(1)
13
12
11
10
9
001aah099
© NXP B.V. 2009. All rights reserved.
4B
4A
4Y
3B
3A
74LV132
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