A25LQ032N-F AMIC, A25LQ032N-F Datasheet
A25LQ032N-F
Specifications of A25LQ032N-F
Related parts for A25LQ032N-F
A25LQ032N-F Summary of contents
Page 1
... P36 and P37: ID code error correction 0.3 ata Retention and Endurance value from Max. P44: Change D to Min. PRELIMINARY (October, 2010, Version 0.3) A25LQ032 Series with 100MHz Uniform 4KB Sectors Issue Date April 16, 2009 May 5, 2010 September 21, 2010 October 11, 2010 AMIC Technology Corp. Remark Preliminary ...
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... The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction sector at a time, using the Sector Erase instruction A25LQ032 Series Figure 1b. SOP16 Connections HOLD ( ( ( ( not use AMIC Technology Corp. ...
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... Chip Select Input (1) Data Output (Data Input Output 1) Write Protect Input (Data Input Output 2) Ground Don’t Use Don’t Use Don’t Use Don’t Use (1) Data Input (Data Input Output 0) Serial Clock Input 2 A25LQ032 Series (2) (2) AMIC Technology Corp. ...
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... Address register and Counter PRELIMINARY (October, 2010, Version 0.3) High Voltage Generator I/O Shift Register 256 Byte Data Buffer FFFFF (8M) 00000h 000FFh 256 Byte (Page Size) X Decoder AMIC Technology Corp. 3 A25LQ032 Series 64 OTP bytes Status Register Size of the memory area ...
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... HOLD S ) pin is low, the DO pin will be at high HOLD ) pin is active low. HOLD ) pin function is not available since this pin is . See figure 1a and 1b for the pin configuration of 3 AMIC Technology Corp. . See figure 1a and ) pin is brought low, HOLD ) pin is ...
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... The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= MSB DO 5 A25LQ032 Series MSB AMIC Technology Corp. ...
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... Serial Clock ) signal, provided that this coincides with Serial Clock S ) goes High while the device is in the Hold HOLD ) High, and then to drive Chip S ) Low. This prevents the device from going back to Hold Condition (non-standard use) AMIC Technology Corp. function is only S ) ...
Page 8
... BP1, BP0) bits, Sector Protect (SEC) bit, Top/Bottom (TB) bit, All Protect (APT), Complement Protect (CMP) bit and Status Register Protect (SRP1, SRP0) bits to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the AMIC Technology Corp. . The CC2 ) can provide PUW ...
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... AMIC Technology Corp. Portion None Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/64 Lower 1/32 Lower 1/16 Lower 1/8 Lower 1/4 ...
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... None None 4092KB 4088KB 4080KB 4064KB 4032KB 4092KB 4088KB 4080KB 4064KB 4032KB AMIC Technology Corp. Portion All Lower 63/64 Lower 31/32 Lower 15/16 Lower 7/8 Lower 3/4 Lower 1/2 Upper 63/64 Upper 31/32 Upper 15/16 Upper 7/8 Upper 3/4 ...
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... FF000h FFFFFh 240 F0000h F0FFFh 239 EF000h EFFFFh 224 E0000h E0FFFh 223 DF000h DFFFFh 208 D0000h D0FFFh 207 CF000h CFFFFh 192 C0000h C0FFFh 191 BF000h BFFFFh 176 B0000h B0FFFh 175 AF000h AFFFFh 160 A0000h A0FFFh AMIC Technology Corp. ...
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... A25LQ032 Series Sector Address range 63 3F000h 3FFFFh 48 30000h 30FFFh 47 2F000h 2FFFFh 32 20000h 20FFFh 31 1F000h 1FFFFh 16 10000h 10FFFh 15 0F000h 0FFFFh 4 04000h 04FFFh 3 03000h 03FFFh 2 02000h 02FFFh 1 01000h 01FFFh 0 00000h 00FFFh AMIC Technology Corp. ...
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... Register cycle, Program cycle or Erase cycle are ignored, and (FAST_READ_QUAD the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. 12 A25LQ032 Series S ) must be driven High exactly at a byte boundary must driven High when the number being driven Low is an AMIC Technology Corp ...
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... EBh 3 4Bh or 3 48h 42h 3 02h 3 A2h 3 32h 3 20h 3 D8h or 3 52h C7h or 0 60h B9h 0 9Fh 0 (7) 90h 1 0 ABh 0 A3h 0 FFh or 0 FFFFh AMIC Technology Corp. Data Bytes ∞ ∞ ∞ ∞ ( ∞ (2) ( ∞ ( ∞ (3) ( ∞ ∞ 256 (5) ...
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... ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first (8) This instruction is recommended when using the Dual or Quad “Continuous Read Mode” features. See page 22&25 for more information. PRELIMINARY (October, 2010, Version 0.3) AMIC Technology Corp. 14 A25LQ032 Series ...
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... Quad Input Fast Program (QIFP) instruction completion ﹣ Program OTP (POTP) in ﹣ Sector Erase (SE) instruction completion ﹣ Block Erase (BE) instruction completion ﹣ Chip Erase (CE) instruction completion Instruction (04h) DI High Impedance DO 15 A25LQ032 Series S ) Low, sending the instruction code, and then S ) High struction completion 6 7 AMIC Technology Corp. ...
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... Please refer to table 1 for more details. The factory default setting for CMP A25LQ032 Series in AC characteristics). All, none pin are enabled. When QE is set to 1, the HOLD pin become IO and IO . This bit can be set with 2 3 AMIC Technology Corp. W pin and W pin ...
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... Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence Instruction (05h or 35h) DI High Impedance DO PRELIMINARY (October, 2010, Version 0.3) 3. When APT is 1 and CMP is 1, all BP2, BP1, BP0 will be set to 0 after power-on Status Register Out MSB 17 A25LQ032 Series Status Register Out MSB AMIC Technology Corp. ...
Page 19
... Status Register is permanently protected. The values in the CMP, One Time Program APT, SRP1, SRP0, SEC, TB, BP2, BP1, BP0 bits cannot be changed. 18 A25LQ032 Series driven High, the self-timed ) pin to disable writes to the Status Register. Factory Description pin is high. Status Register is Writable (if the WREN AMIC Technology Corp initiated ...
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... High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress 24-Bit Address MSB 19 A25LQ032 Series High. Chip Select ( 0 Data Out 2 Data Out MSB AMIC Technology Corp. ) can be driven ...
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... Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress 24-Bit Address MSB Data Out MSB 20 A25LQ032 Series S ) can be driven High at any time during data Data Out MSB AMIC Technology Corp High. 7 MSB ...
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... AC Characteristics 24-Bit Address MSB DIO switches from input to output MSB Data Out 1 Data Out 2 21 A25LQ032 Series and MSB MSB Data Out 3 Data Out 4 AMIC Technology Corp. pins should 1 ...
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... DIO switches from input to output MSB MSB Data Out 2 Data Out 3 Data Out 1 22 A25LQ032 Series Read” Mode and S is asserted low. If the S is raised and then lowered) requires the MSB MSB Data Out 4 Data Out 5 AMIC Technology Corp. the next S ...
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... Address DIO switches from input to output M7 MSB Data Out 1 Note: Address bits A23 to A22 are Don’t Care, for A25LQ032. PRELIMINARY (October, 2010, Version 0. MSB MSB Data Out 2 Data Out 3 Data Out 4 23 A25LQ032 Series 7 MSB Data Out 5 AMIC Technology Corp. ...
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... However, the IO pins should be instruction, the high-impedance prior to the falling edge of the first data out clock. (See AC Characteristics 24-Bit Address MSB switches from input to output Data Out 1Data Out 2Data Out 3Data Out 4 24 A25LQ032 Series AMIC Technology Corp. ...
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... A25LQ032 Series Read” Mode S is asserted low. If the S is raised and then lowered) requires the IO Switches from Input to Output M7-0 Dummy Dummy Data out 1 Data out Switches from Input to Output Data out 1 Data out 2 AMIC Technology Corp. and the next ...
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... Register cycle is in progress, is rejected without having any C effect on the cycle that is in progress 24-Bit Address MSB MSB Data Out 1 Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64) 26 A25LQ032 Series High. Chip Select ( ) can be driven High MSB MSB Data Out n AMIC Technology Corp. ...
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... While PP rejected without having any effect on the cycle that is in progress 24-Bit Address MSB Data Byte MSB Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64) 27 A25LQ032 Series Data Byte MSB Data Byte MSB AMIC Technology Corp. 7 MSB ...
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... Figure 16. How to permanently lock the 64 OTP bytes Byte Byte Byte PRELIMINARY (October, 2010, Version 0.3) 64 Data Byte Bit Bit Bit Bit Bit Bit A25LQ032 Series OTP Control Byte Byte Byte 62 63 When bit 0 =0 Bit Bit the OTP bytes 1 0 become READ only AMIC Technology Corp. ...
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... Data Byte MSB Note: Address bits A23 to A22 are Don’t Care, for A25LQ032. 29 A25LQ032 Series S ) must be driven High after the eighth bit of the driven High, the self-timed Data Byte MSB Data Byte 256 MSB AMIC Technology Corp initiated. While PP ...
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... BP2, BP1, BP0) bits (see Table 1) is not executed 24-Bit Address MSB Data In 2 Data In 3 Data MSB MSB MSB 30 A25LQ032 Series S ) must be driven High after the eighth bit driven High, the self-timed ) is initiated. While Data In 5 Data In 256 MSB MSB AMIC Technology Corp. ...
Page 32
... BP2, BP1, BP0) bits (see Table 1) is not executed 24-Bit Address MSB A25LQ032 Series S ) must be driven High after the eighth bit driven High, the self-timed ) is initiated. While PP Byte 1 Byte 2 Byte 3 Byte MSB 55 Byte 253 Byte 254Byte 255 Byte 256 AMIC Technology Corp. ...
Page 33
... Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, BP0) bits (see table 1) is not executed Instruction (20h) 24-Bit Address MSB 32 A25LQ032 Series ) is initiated. While the Sector Erase cycle AMIC Technology Corp ...
Page 34
... A Block Erase (BE) instruction applied to a page which is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, BP0) bits (see table 1) is not executed Instruction (D8h or 52h MSB 33 A25LQ032 Series ) is initiated. While the Block Erase cycle is in progress 24-Bit Address AMIC Technology Corp ...
Page 35
... Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) instruction is ignored if one, or more, sectors/blocks are protected Instruction (C7h or 60h) 34 A25LQ032 Series AMIC Technology Corp. ...
Page 36
... Instruction (B9h) Stand-by Mode 35 A25LQ032 Series S ) Low, followed by the instruction code must be driven Low for S ) must be driven High after the eighth bit of the driven High, it requires a delay Deep Power-down Mode AMIC Technology Corp. DP and the Deep CC2 ...
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... S and execute instructions. ) Low. Device Identification Memory Type 40h Manufacture ID 36 A25LQ032 Series S ) High at any time during data output driven High, the device is put in the Memory Capacity 16h (A25LQ032 Memory Type Memory Capacity AMIC Technology Corp ...
Page 38
... The manufacturer identification is assigned by JEDEC, and has the value 37h for AMIC. The device identification is assigned by the device manufacturer, and has the value 15h for A25LQ032. Any Read Electronic Manufacturer ID & Device ID (REMS) ...
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... Dummy Bytes MSB MSB Deep Power-down Mode 38 A25LQ032 Series ) High after the Electronic Signature has been read driven Low, cause the driven High, the device is put in the , and Chip Select ( RES2 (max), as specified in AC RES2 t RES2 Stand-by Mode AMIC Technology Corp ...
Page 40
... Stand-by Power mode is delayed by t and Chip Select ( as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 39 A25LQ032 Series t RES1 Stand-by Mode S ) must remain High for at least t AMIC Technology Corp. , RES1 (max), RES1 ...
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... SPI standby current (I addition, Write Enable instruction (06h) and Power Down instruction (B9h) will also release the device from HPM mode back to standard SPI standby state Dummy Bytes MSB 40 A25LQ032 Series t RES2 0 0 High Performance Current AMIC Technology Corp CC1 ...
Page 42
... Continuous Read Mode Reset instruction even the controller resets while A25LQ032 is set to Continuous Mode Read. Mode Bit Reset for Quad I FFh Do not care Do not care Do not care 41 A25LQ032 Series Mode Bit Reset for Dual I/O FFh AMIC Technology Corp. ...
Page 43
... The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. feed. Each device in a system should CC rail decoupled by a suitable capacitor close to CC drops from the operating voltage, CC Full Device Access time AMIC Technology Corp. has risen above CC , all operations are WI ...
Page 44
... The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). PRELIMINARY (October, 2010, Version 0.3) Parameter 43 A25LQ032 Series Min. Max. Unit μ 2.3 2.5 V AMIC Technology Corp. ...
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... Exposure to Absolute Maximum Rating conditions +2.0V CC for extended periods may affect device reliability. Refer also to the AMIC SURE Program and other relevant quality documents. Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on ...
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... –100µA OH Parameter Input Levels A25LQ032 Series Min open open –0.5 0. –0.2 CC Min. Max 0. 0. Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. Max. Unit ± 2 µA ± 2 µA 15 µA 15 µ Unit ...
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... Only applicable as a constraint for WRSR instruction when Status Register Protect bits (SRP1, SRP0) = (0, 1) PRELIMINARY (October, 2010, Version 0.3) Parameter 3 (peak to peak) 3 (peak to peak A25LQ032 Series Min. Typ. Max. Unit D.C. 100 MHz D.C. 50 MHz 0.1 V/ns 0.1 V/ 100 ns 3 µs 1 µs 1 µ 1 0.4 1 280 ms 0 AMIC Technology Corp. ...
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... Figure 32. Serial Input Timing S tCHSL C tDVCH DI DO Figure 33. Write Protect Setup and Hold Timing during WRSR when (SRP1, SRP0 tWHSL PRELIMINARY (October, 2010, Version 0.3) tSLCH tCHDX MSB IN High Impedance High Impedance 47 A25LQ032 Series tSHSL tSHCH tCHSH tCHCL tCLCH LSB IN tSHWL AMIC Technology Corp. ...
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... Hold Timing Figure 34 HOLD Figure 35. Output Timing ADDR.LSB IN tCLQV tCLQX tCLQX DO PRELIMINARY (October, 2010, Version 0.3) tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 48 A25LQ032 Series tHHCH tHHQX tCL LSB OUT tQLQH tQHQL AMIC Technology Corp. tSHQZ ...
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... Mbit (4KB uniform sectors) 080 = 8 Mbit (4KB uniform sectors) 016 = 16 Mbit (4KB uniform sectors) 032 = 32 Mbit (4KB uniform sectors) Quad SPI Operation Q = Support Quad SPI Operation Blank = Do not support Quad SPI Operation Device Voltage L = 2.7-3.6V Device Type A25 = AMIC Serial Flash AMIC Technology Corp. ...
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... Ordering Information Part No. Speed (MHz) A25LQ032-F A25LQ032-UF A25LQ032M-F 100 A25LQ032M-UF A25LQ032N-F A25LQ032N- for industrial operating temperature range: -40°C ~ +85°C PRELIMINARY (October, 2010, Version 0.3) Active Read Program/Erase Current Current Max. (mA) Max. (mA A25LQ032 Series Standby Current Package Max. (μA) 8 Pin Pb-Free DIP (300 mil) ...
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... Dimensions in mm Min Nom Max - - 4.57 0. 3.25 3.30 3.45 0.36 0.46 0.56 1.27 1.52 1.78 0.81 0.99 1.17 0.20 0.25 0.33 8.89 9.14 9.40 7.37 7.62 8.00 6.45 6.60 6.76 - 2. 8.76 - 9.78 0.41 0.53 0.66 AMIC Technology Corp. unit: inches/mm ...
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... E 7.70 7.90 E 5.18 5. 1.27 BSC L 0.50 0.65 θ 0° - Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads 52 A25LQ032 Series C θ L Max 2.16 0.25 1.91 0.48 0.25 5.33 8.10 5.38 0.80 8° AMIC Technology Corp. unit: mm ...
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... L 0.016 0.050 θ 8° 0° gate burrs. 53 A25LQ032 Series C o θ L Dimensions in mm Min Max 2.36 2.65 0.10 0.30 0.41 Typ. 0.20 Typ. 10.10 10.50 7.39 7.60 1.27 Typ. 10.01 10.64 0.40 1.27 8° 0° AMIC Technology Corp. unit: inches/mm ...