A25LQ032N-F AMIC, A25LQ032N-F Datasheet - Page 20

• Manufacturer Part Number: A25LQ032N-F
• Description: 58T1295
• Manufacturer: AMIC

Specifications of A25LQ032N-F

• Memory Type: Flash
• Memory Size: 32Mbit
• Memory Configuration: 32M X 1
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 16
• Rohs Compliant: Yes

Read Data Bytes (READ)
The device is first selected by driving Chip Select (
The instruction code for the Read Data Bytes (READ)
instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on
Serial Data Output (DO), each bit being shifted out, at a
maximum frequency f
(C).
The instruction sequence is shown in Figure 8. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
PRELIMINARY
DO
DI
S
C
(October, 2010, Version 0.3)
Note: Address bits A23 to A22 are Don’t Care, for A25LQ032.
R
, during the falling edge of Serial Clock
0 1
High Impedance
Instruction (03h)
2 3 4
5 6
7
MSB
23 22 21
8
S
) Low.
9
24-Bit Address
10
19
3 2 1
28 29 30 31 32 33 34 35 36 37 38 39
therefore, be read with a single Read Data Bytes (READ)
instruction. When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by
driving Chip Select (
High at any time during data output. Any Read Data Bytes
(READ) instruction, while an Erase, Program or Write cycle is
in progress, is rejected without having any effects on the
cycle that is in progress.
0
MSB
7
6 5 4 3 2 1 0
Data Out 1
S
) High. Chip Select (
AMIC Technology Corp.
A25LQ032 Series
7
Data Out 2
S
) can be driven