A25LQ032N-F AMIC, A25LQ032N-F Datasheet - Page 13

• Manufacturer Part Number: A25LQ032N-F
• Description: 58T1295
• Manufacturer: AMIC

Specifications of A25LQ032N-F

• Memory Type: Flash
• Memory Size: 32Mbit
• Memory Configuration: 32M X 1
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 16
• Rohs Compliant: Yes

INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input(s) IO
first rising edge of Serial Clock (C) after Chip Select (
driven Low. Then, the one-byte instruction code must be
shifted in to the device, most significant bit first, on Serial Data
Input(s) IO
edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by dummy bytes (don’t
care), or by a combination or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Data Bytes at Higher Speed
by Dual Output (FAST_READ_DUAL_OUTPUT), Read Data
Bytes at Higher Speed by Dual Input and Dual Output
(FAST_READ_DUAL_INPUT_OUTPUT) , Read Data Bytes at
Higher
_OUTPUT), Read Data Bytes at Higher Speed by Quad Input
and Quad Output (FAST_READ_QUAD_INPUT_OUTPUT),
Read OTP (ROTP), Read Identification (RDID), Read
Electronic Manufacturer and Device Identification (REMS),
PRELIMINARY
Speed
0
(IO
1
, IO
(October, 2010, Version 0.3)
by
2
, IO
0
Quad
(IO
3
), each bit being latched on the rising
1
, IO
Output
2
, IO
3
) is (are) sampled on the
(FAST_READ_QUAD
S
) is
12
Read Status Register (RDSR) or Release from Deep
Power-down, Read Device Identification and Read Electronic
Signature (RES) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip Select (
can be driven High after any bit of the data-out sequence is
being shifted out.
In the case of a Page Program (PP), Program OTP (POTP),
Dual Input Fast Program (DIFP), Quad Input Fast Program
(QIFP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR), Write Enable (WREN), Write
Disable (WRDI) or Deep Power-down (DP) instruction, Chip
Select (
otherwise the instruction is rejected, and is not executed. That
is, Chip Select (
clock pulses after Chip Select (
exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
S
) must be driven High exactly at a byte boundary,
S
) must driven High when the number of
AMIC Technology Corp.
A25LQ032 Series
S
) being driven Low is an
S
)