P89LV51RD2BBC NXP Semiconductors, P89LV51RD2BBC Datasheet - Page 43

• Manufacturer Part Number: P89LV51RD2BBC
• Description: MCU 8-Bit 89LV 80C51 CISC 64KB Flash 3.3V 44-Pin TQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89LV51RD2BBC

• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
Fig 16. SPI master-slave interconnection
CLOCK GENERATOR
SPI
and slave SPI devices. The SPICLK pin is the clock output and input for the master and
slave modes, respectively. The SPI clock generator will start following a write to the
master devices SPI data register. The written data is then shifted out of the MOSI pin on
the master device into the MOSI pin of the slave device. Following a complete
transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is
set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and
the Serial Port Interrupt Enable bit (ES) are both set.
An external master drives the Slave Select input pin, SS/P1[4], low to select the SPI
module as a slave. If SS/P1[4] has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock.
show the four possible combinations of these two bits.
Table 28.
Bit addressable; reset source(s): any reset; reset value: 0000 0000B.
Table 29.
Bit
7
6
5
4
3
Bit
Symbol
8-BIT SHIFT REGISTER
MSB master LSB
SPCTL - SPI control register (address D5H) bit allocation
SPCTL - SPI control register (address D5H) bit descriptions
Symbol
SPIE
SPEN
DORD
MSTR
CPOL
SPIE
7
Rev. 05 — 15 December 2009
SPEN
Description
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit. When set enables SPI.
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
Master/slave select. 1 = master mode, 0 = slave mode.
Clock polarity. 1 = SPICLK is high when idle (active LOW), 0 = SPICLK
is low when idle (active HIGH).
6
MISO
MOSI
SPICLK
SS
V
DD
DORD
5
SPICLK
V
P89LV51RB2/RC2/RD2
MISO
MOSI
SS
MSTR
SS
4
8-bit microcontrollers with 80C51 core
CPOL
3
8-BIT SHIFT REGISTER
MSB slave LSB
CPHA
2
Figure 17
© NXP B.V. 2009. All rights reserved.
PSC1
002aaa528
1
and
Figure 18
PSC0
43 of 76
0