MT90870AG Zarlink, MT90870AG Datasheet - Page 47

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

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11.2
The MT90870 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an Instruction
Register and three Test Data Registers.
11.2.1
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning.
11.2.2
11.2.2.1
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the MT90870 core logic.
11.2.2.2
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
11.2.2.3
The JTAG device ID for the MT90870 is 0087014B
Version, Bits <31:28>:
Part No., Bits <27:12>:
Manufacturer ID, Bits <11:1>: 0001 0100 101
Header, Bit <0> (LSB):
11.3
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port
is connected either to the Instruction Register or to a Test Data Register. Both registers are described in
a Section 11.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This
pin is internally pulled to V
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on
the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo
output is set to a high impedance state.
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled to V
when not driven from an external source.
Boundary Scan Description Language (BSDL) File
TAP Registers
Test Instruction Register
Test Data Registers
The Boundary-Scan Register
The Bypass Register
The Device Identification Register
0000
1
0000 1000 0111 0000
DD_IO
when not driven from an external source.
Zarlink Semiconductor Inc.
MT90870
H
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47
Data Sheet
DD_IO