MT90870AG Zarlink, MT90870AG Datasheet - Page 63

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.10
13.10.1
Address 00C3h.
Local BER Start Send Register defines the output channel and the stream in which the BER sequence starts to
be transmitted. The LBSSR register is configured as follows:
13.10.2
Address 00C4h
Local BER Transmit Length Register (LTXBLR) defines how many channels the BER sequence will be transmitted
during each frame. The LTXBLR register is configured as follows:
15-8
Bit
15-12
Backplane Output Advancement For
11-8
Bit
7-0
2 Mb/s, 4 Mb/s, 8 Mb/s & 16 Mb/s
Local Bit Error Rate (BER) Registers
Reserved
clock Rate 131.072 MHz
Local Transmit BER Length Register (LTXBLR)
Name
Local BER Start Send Register (LBSSR)
LBSCA(7:0)
LBSSA(3:0)
Table 30 - Backplane Output Advancement (BOAR) Programming Table
Reserved
0 (Default)
-4 cycles
-6 cycles
-2 cycle
Name
Table 32 - Local Transmit BER Length Register (LTXBLR) Bits
Reset
0
Table 31 - Local BER Start Send Register (LBSSR) Bits
Reserved.
Reset
0
0
0
Reserved.
Local BER Send Stream Address Bits.
The binary value of these bits refers to the Local output stream
which carries the BER data.
Local BER Send Channel Address Bits.
The binary value of these bits refers to the Local output channel in
which the BER data starts to be sent.
Zarlink Semiconductor Inc.
MT90870
Advancement For 32 Mb/s
63
clock Rate 131.072 MHz
Backplane Output
0 (Default)
-1 cycle
-2 cycle
-3 cycle
Description
Description
Advancement Bits
BOA1
Corresponding
0
0
1
1
Data Sheet
BOA0
0
1
0
1