MT9092AP Zarlink, MT9092AP Datasheet - Page 10

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

MT9092
Data Sheet
control bits reside in the DSP Control Register at address 1Eh. When either of these bits are low, their respective
paths function normally.
HDLC
The High-level Data Link Control (HDLC) block is located, functionally, between the serial ST-BUS port and the
serial Microcontroller port. This functional block handles the bit oriented protocol requirements of layer 2 X.25
packet switching and Q.921 link access protocols defined by CCITT. The HDLC is dedicated to D-Channel
operation at 16 kb/s and offers buffered access to the serial D-Channel data through separate 19 byte transmit and
receive FIFOs.
The HDLC generates and detects the flags, various link channel states and abort sequences as well as performing
a cyclic redundancy check on data packets according to the CCITT defined polynomial. Lastly, the protocol
functions may be disabled to provide transparent access, of the serial port D-Channel, to the microport.
A power up reset (PWRST, pin 6) or a software reset via RST (address 0Fh) will cause the HDLC transceiver to be
initialized. This results in the transmitter and receiver being disabled and all HDLC registers defaulting to their
power reset values.
HDLC Frame Structure
A valid HDLC frame begins with an opening flag, contains at least 16 bits of address, control or information, ends
with a 16 bit FCS followed by a closing flag. Data formatted in this manner is also referred to as a "packet". Refer to
Figure 4.
FLAG
DATA FIELD
FCS
FLAG
One
n Bytes
Two
One
Byte
(nŠ2)
Bytes
Byte
Figure 4 - Frame Format
Flag Sequence
All HDLC frames start and end with a unique sequence of 8 bits. This sequence is 0111 1110 (7Eh). The closing flag
of one frame can be the opening flag of the next frame. The transmitter generates flags and appends them to the
packet to be transmitted. The receiver searches the incoming data stream for flags on a bit-by-bit basis to establish
frame synchronization. The receiver uses flags for synchronization only and does not transfer them to the Rx FIFO.
Address Field
The address field consists of one or two 8-bit bytes directly following the opening flag. Address, Control and
Information fields are known collectively as the Data field.
Control Field
The control field consists of one 8-bit byte directly following the address field. The HDLC does not distinguish
between the control field and the information field.
Information Field
The information field immediately follows the control field and consists of N bytes of data where one byte contains 8
bits. A packet does not need to contain an information field to be valid. The HDLC does not distinguish between the
control field and the information field.
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Zarlink Semiconductor Inc.