MT9092AP Zarlink, MT9092AP Datasheet - Page 23

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Register Summary
This section contains a complete listing of the HPhone-II register addresses, the control/status bit mapping
associated with each register and a definition of the function of each control/status bit. The Register Summary may
be used for future reference to review each of the control/status bit definitions without the need to locate them in the
text of the functional block descriptions.
HDLC Address Recognition Register 1
HDLC Address Recognition Register 2
HDLC Transmit/Receive FIFO Register
Adr 16-11
Adr 10
A1EN
Adr 26-20
A2EN
The Transmitter FIFO is 19 words deep. Each word consists of 8 bits of data from the internal data bus and 2 status bits from CONTROL Register 1
(EOP and FA). If there is data in the Tx FIFO then the lowest data byte in it is loaded into an output shift register for transmission, and the remaining
data shifts down by one word position (Tx FIFO read). A write to a full Tx FIFO will update the top byte only.
The receiver FIFO is 19 words deep. During a receiver write, the last 8 bits of a shift register buffer and two status bits are loaded into Rx FIFO. Data
shifts down into the Rx FIFO following a microprocessor read. A write to a full RX FIFO will not update the FIFO.
A six bit mask used to interrogate the first byte of the received address. Adr16 is MSB. In the Q.921 specification these bits are
This bit is used in address comparison if a seven bit address is being checked for (Control bit Seven of Control Register 2 is set). In the
When this bit is high, this six (or seven) bit mask is used in address comparison of the first address byte. If address recognition is
A seven bit mask used to interrogate the second byte of the received address. Adr26 is MSB. This mask is ignored (as well as first byte
When this bit is high this seven bit mask is used in address comparison of the second address byte. If address recognition is enabled,
defined to be Sapi5-0.
Q.921 specification this bit is defined to be C/R (Command/Response).
enabled, any packet failing the address comparison will not be stored in the RX FIFO. A1EN must be high for All-call (1111111)
address recognition for single byte address. When this bit is low, this bit mask is ignored in address comparison.
mask) if an All call address (1111111) is received. In the Q.921 specification these bits are defined to be Tei6-0.
any packet failing the address comparison will not be stored in the RX FIFO. A2EN must be high for All-call address recognition.
When this bit is low, this bit mask is ignored in address comparison.
Adr16
Adr26
D7
7
7
7
Adr15
Adr25
D6
6
6
6
Adr14
Adr24
D5
5
5
5
Adr13
Adr23
D4
4
4
4
Zarlink Semiconductor Inc.
Adr12
Adr22
D3
3
3
3
MT9092
Adr11
Adr21
23
D2
2
2
2
Adr10
Adr20
D1
1
1
1
ADDRESS = 00h WRITE/READ VERIFY
ADDRESS = 01h WRITE/READ VERIFY
A1EN
A2EN
D0
0
0
0
ADDRESS = 02h WRITE/READ
Power Reset Value
Power Reset Value
Power Reset Value
Not Applicable
0000 0000
0000 0000
Data Sheet