MT9092AP Zarlink, MT9092AP Datasheet - Page 14

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Address Recognition
When Adrec (HDLC Control Register 1, address 03h) is low all valid received packets, regardless of the address
field information, are loaded into the Rx FIFO.
If address recognition is required, Receive Address Recognition Registers 1 and/or 2 (addresses 00h and 01h
respectively) are loaded with the desired address comparison information, the Adrec bit is set high and A1EN and
A2EN are set as required. Bit 0 (A1EN and A2EN) of both recognition registers is used as an enable for that byte.
When either of these bits are low their respective address mask information is ignored. In this way either or both of
the first two received bytes can be compared to the expected mask values. Only those packets passing the
appropriate comparison test will be loaded into the Rx FIFO. The appropriate comparison test (single/dual byte
address, All-call) is defined by the logic state of bit 0 of the first byte received after the opening flag.
Bit 0 of the first received address byte (address extension bit) is monitored to determine if a single or dual byte
address is being received.
1.
2.
In CCITT Q.921 parlance the Adr11 - Adr16 bits are defined as Sapi0 - Sapi5 (Service Access Point Identifier n).
Adr10 is defined as C/R (Command/ Response). Adr20 - Adr26 are defined as Tei0 - Tei6 (Terminal Endpoint
Identifier n).
Receive Byte Status
As each received packet byte is written into the Rx FIFO two bits are appended to indicate the status of that byte.
As these bytes are read from the Rx FIFO the status bits are made available to the microprocessor in the HDLC
Status Register (address 04h) as RxBS1 and RxBS2. Since the information contained in RxBS1 & RxBS2 pertains
to the byte about to be read from the Rx FIFO, it is important that this information be read before reading the data
byte from the FIFO. RxBS1 and RxBS2 are encoded as shown in Table 2. A good packet indication means a good
FCS and no frame abort whereas a bad packet indication means either an incorrect FCS or a frame abort occurred.
Receive FIFO Status
The receive FIFO is 19 bytes deep (address 02h). As data is loaded into (from the serial port) and extracted from
(via the microport) the Rx FIFO the present 'fill state' can be monitored using the Rxstat1 and Rxstat2 bits found in
the HDLC Status Register (address 04h). These states are encoded as shown in Table 2. Note that the FIFO filling
threshold, where an interrupt (RxFf if unmasked) will occur, can be set to a high level 15 (default) or to a low level 5
by the Flrx bit in the HDLC Control Register 2 (address 05h).
In the case of an Rx FIFO overflow, an attempt by the receiver to write data into an already full FIFO, the receiver is
disabled causing it to stop writing to the Rx FIFO. The remainder of the current receive packet is therefore ignored.
The receiver will be re-enabled when the next flag is detected but will overflow again if the Rx FIFO level has not
been reduced to less than full. If two 'first byte' (RxBS1 and RxBS2) conditions are observed in the FIFO without an
intervening 'last byte' then an overflow occurred for the first packet.
If the address extension bit is 1 then a single byte address is being received. If A1EN is high the stored bit
If the address extension bit is 0 then a two byte address is being received and the six most significant bits
mask (Adr11 - Adr16 and sometimes Adr10) is compared to the received first address byte. Any packet
failing this address comparison will not be stored in the Rx FIFO except for the All-call condition. A1EN
must be set high for a single-byte All-call (11111111) address to be recognized. The second mask byte is
ignored. Seven bits of address comparison may be realized for single byte recognition by setting the
SEVEN bit (address 05h) high. This mode will then include Adr10 as part of the mask information. The first
received byte must also have bit 0 set to a 1 indicating single byte addressing.
of the first received byte are compared. The seven most significant bits of the second received byte are
compared (Adr20 - Adr26, note A2EN must be set high also). Any packet failing this address comparison
will not be stored in the Rx FIFO. An All-call condition (1111111x) is also monitored for in the second
received address byte and, if found, the first and second byte masks are ignored (not compared with the
mask byte). Packets addressed with All-call are written into the Rx FIFO.
Zarlink Semiconductor Inc.
MT9092
14
Data Sheet