MT9092AP Zarlink, MT9092AP Datasheet - Page 12

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Go-Ahead
A go-ahead is defined as the pattern ‘011111110’ (contiguous 7F’s) and is the occurrence of a frame abort sequence
followed by a zero, outside of the boundaries of a normal packet. Being able to distinguish a proper (in packet)
frame abort sequence from one occurring outside of a packet allows a higher level of signalling protocol which is not
part of the HDLC specifications.
Transmitter
Following initialization and enabling, via the HTxEN bit (address 03h), the transmitter is in the Idle Channel State
(Mark Idle). Interframe time fill may be selected by setting the Mark Idle bit (address 03h) high. The transmitter
remains in its programmed state until data is written to the Tx FIFO. The transmitter will then proceed as follows:
1)
2)
To assist in loading multiple packets into the transmit FIFO the last packet byte is tagged with either EOP (to
indicate the end of the current packet) or FA. Control Register 1 (address 03h) bits EOP (end of packet) and FA
(frame abort) are set before writing the last packet byte to the Tx FIFO. The act of loading the last packet byte will
then automatically reset the EOP and FA bits. Tx FIFO bytes are continuously transmitted until the FIFO is empty,
by which time an EOP or FA tag should have been encountered by the transmitter.
After the last bit of the EOP byte has been transmitted a 16 bit FCS is sent followed by a closing flag. When multiple
packets of data are loaded into the Tx FIFO only one flag is sent between packets.
When the transmitter encounters a byte tagged FA then a frame abort sequence is sent instead of the tagged byte.
All bytes previous to but not including the tagged byte are sent.
The transmitter returns to its programmed wait state after concluding the transmission of EOP or FA if the Tx FIFO
is empty.
Transmit FIFO Status
The transmit FIFO is 19 bytes deep (address 02h). As data is loaded into (from the microport) and extracted from
(via the serial port) the Tx FIFO the present 'fill state' can be monitored using the Txstat1 and Txstat2 bits found in
the HDLC Status Register (address 04h). These states are encoded as shown in Table 2. Note that the FIFO
emptying threshold, where an interrupt (TxFL if unmasked) will occur, can be set to a low level 4 (default) or to a
high level 14 by the Fltx bit in the HDLC Control Register 2 (address 05h).
A Tx FIFO underrun occurs if the Tx FIFO empties without the occurrence of an EOP or FA tagged byte. A frame
abort sequence is automatically transmitted under this condition.
Transmit Interrupts
The HDLC Interrupt Enable Register (address 06h) is used to select (unmask) only those interrupts which are
deemed important to the microprocessor. After a PWRST or software RST all enable bits will be cleared causing all
interrupts to be masked.
All selected interrupt events will cause the IRQ pin to become active. Unselected interrupt events will not cause IRQ
to become active however, the event will still be represented by the appropriate bit in the HDLC Interrupt Status
Register (address 07h). This register must be read after receiving an IRQ or may be polled at any time. The IRQ
output pin is reset coincident with the first SCLK falling edge following a Command/Address byte which indicates a
microport read of address 07h. Since all interrupts are generated by the occurrence of an HDLC event (i.e., a
transition), this register informs that an event has occurred but does not guarantee that it is still valid. To determine
current validity the HDLC Status Register (address 04h) should be read. Due to the asynchronous nature of the
interrupts an interrupt occurring during a read of the Interrupt Status register will be held until the read cycle is over,
unless it is an interrupt which is already valid.
opening flag and packet data is sent.
opening flag followed by the packet data.
If the transmitter is in the idle state the present byte of ones will be completely transmitted before the
If the transmitter is in the interframe time fill state the flag currently being transmitted will be used as the
Zarlink Semiconductor Inc.
MT9092
12
Data Sheet