ISL23348UFVZ Intersil, ISL23348UFVZ Datasheet - Page 7

• Manufacturer Part Number: ISL23348UFVZ
• Description: IC DGTL POT 4CH 50K 20TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23348UFVZ

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 65 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Operating Specifications
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Serial Interface Specification
V
tShdnRec
(Note 21)
CC,
SYMBOL
Hysteresis
Ramp
SYMBOL
t
t
t
t
t
DCP
V
HD:DAT
SU:STA
HD:STA
SU:DAT
t
t
f
t
C
HIGH
LOGIC
V
V
t
LOW
V
t
BUF
SCL
AA
pin
OL
sp
IH
IL
Wiper Response Time
DCP Recall Time from Shutdown Mode
V
CC ,
Input LOW Voltage
Input HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage
SDA, SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
V
LOGIC
Ramp Rate
PARAMETER
PARAMETER
7
V
CC
= 2.7V to 5.5V, V
For SCL, SDA, A0, A1, A2 unless otherwise noted.
V
V
I
I
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge; both crossing
70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL falling edge crossing 70% of V
SDA entering the 30% to 70% of V
OL
OL
LOGIC
LOGIC
LOGIC
W option; SCL rising edge at the acknowledge bit
after data byte to wiper new position from 10% to
90% of the final value.
U option; SCL rising edge of the acknowledge bit
after data byte to wiper new position from 10% to
90% of the final value.
T option; SCL rising edge of the acknowledge bit
after data byte to wiper new position from 10% to
90% of the final value.
SCL rising edge of the acknowledge bit after ACR
data byte to wiper recalled position and RH
connection
Ramp monotonic at any level
= 3mA, V
= 1.5mA, V
> 2V
< 2V
LOGIC
LOGIC
ISL23348
LOGIC
LOGIC
TEST CONDITIONS
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
> 2V
< 2V
LOGIC
(Continued)
LOGIC
LOGIC
during a STOP
LOGIC
crossing
crossing
LOGIC
LOGIC
LOGIC
LOGIC
window
LOGIC
LOGIC
, until
LOGIC
window
during
to
to
0.05 x V
0.7 x V
0.1 x V
(Note 20)
(Note 20)
1300
1300
MIN
600
600
600
100
0.01
-0.3
MIN
0
0
LOGIC
LOGIC
LOGIC
(Note 8)
(Note 8)
TYP
10
TYP
0.4
1.5
3.5
1.5
0.3 x V
V
0.2 x V
LOGIC
(Note 20)
(Note 20) UNITS
MAX
400
900
0.4
50
MAX
50
LOGIC
LOGIC
August 24, 2011
+ 0.3
FN7903.1
UNITS
V/ms
kHz
µs
µs
µs
µs
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V
V