ISL23348UFVZ Intersil, ISL23348UFVZ Datasheet - Page 8

• Manufacturer Part Number: ISL23348UFVZ
• Description: IC DGTL POT 4CH 50K 20TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23348UFVZ

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 65 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Interface Specification
NOTES:
10. ZS error = V(RW)
11. FS error = [V(RW)
12. DNL = [V(RW)
13. INL = [V(RW)
14.
15. MI =
16. Roffset = RW
18. RINL = [RW
19.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the V
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
17. RDNL = (RW
8. Typical values are for T
9. LSB = [V(RW)
SYMBOL
TC
TC
t
voltage when changing from one tap to an adjacent tap.
hex respectively.
Roffset = RW
first followed by the V
t
HD:STO
SU:STO
t
t
t
SU:A
HD:A
Cb
t
V
R
DH
t
R
F
=
|
=
RW
Max V RW
----------------------------------------------------------------------------- -
[
------------------------------------------------------ -
Max Ri
127
i
(
i
i
– (MI • i) – RW
Ri +25°C
STOP Condition Set-up Time
STOP Condition Hold Time for Read
or Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
A1, A0, A2 Setup Time
A1, A0, A2 Hold Time
127
0
– RW
127
(
i
– i • LSB – V(RW)
– RW
V RW
/
– V(RW)
(
(
MI, when measuring between RW and RL.
(
0
) Min Ri
/
– V(RW)
127
/
MI, when measuring between RW and RH.
–
LSB.
i-1
)
0
i
i
|
) Min V RW
)
(
CC
– V
/
+25°C
/
A
–
MI -1, for i = 8 to 127.
i-1
127. MI is a minimum increment. RW
)
.
PARAMETER
= +25°C and 3.3V supply voltages.
(
CC
]
0
/
]
LSB-1, for i = 1 to 127. i is the DCP register setting.
]
/
)
/
0
127. V(RW)
(
]
LSB.
]
)
/
×
8
)
MI, for i = 8 to 127.
(
0
---------------------
+165°C
]/LSB for i = 1 to 127
10
)
i
LOGIC
6
)
×
127
---------------------
+165°C
10
and the V
and V(RW)
for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
6
For SCL, SDA, A0, A1, A2 unless otherwise noted.
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge; both
crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
window. I
V
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
Before START condition
After STOP condition
LOGIC
for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
CC
0
supplies at the same time. If this is not possible, it is recommended to ramp-up the V
are V(RW) for the DCP register set to 7f hex and 00 hex respectively. LSB is the incremental
< 2V
OL
ISL23348
127
= 3mA, V
TEST CONDITIONS
and RW
LOGIC
LOGIC
LOGIC
LOGIC
0
are the measured resistances for the DCP register set to 7f hex and 00
> 2V. I
OL
LOGIC
= 0.5mA,
LOGIC
LOGIC
LOGIC
, to
,
(Continued)
20 + 0.1 x Cb
20 + 0.1 x Cb
(Note 20)
1300
MIN
600
600
600
10
0
(Note 8)
TYP
(Note 20)
MAX
250
250
400
August 24, 2011
FN7903.1
UNITS
LOGIC
pF
ns
ns
ns
ns
ns
ns
ns