LPC1754FBD80,518 NXP Semiconductors, LPC1754FBD80,518 Datasheet - Page 56
LPC1754FBD80,518
Manufacturer Part Number
LPC1754FBD80,518
Description
IC MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheet
1.LPC1759FBD80551.pdf
(74 pages)
Specifications of LPC1754FBD80,518
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC1700
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
52
Interface Type
CAN/I2C/SPI/UART/USB
On-chip Adc
6-chx12-bit
Number Of Timers
4
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1754FBD80,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1754FBD80,518
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
11.9 SPI
Table 16.
T
[1]
[2]
Symbol
T
t
t
t
SPI slave
t
t
t
T
t
SPI master
t
t
t
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIQV
SPIOH
SPIDSU
SPIDH
SPIQV
SPIOH
amb
Fig 21. SPI master timing (CPHA = 1)
cy(PCLK)
SPICYC
T
processor clock CCLK.
Timing parameters are measured with respect to the 50 % edge of the clock PCLK and the 10 % (90 %)
edge of the data signal (MOSI or MISO).
=
SPICYC
40
= (T
Dynamic characteristics of SPI pins
C to +85
SCK (CPOL = 0)
SCK (CPOL = 1)
Parameter
PCLK cycle time
SPI cycle time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
cy(PCLK)
All information provided in this document is subject to legal disclaimers.
MOSI
MISO
n) 0.5 %, n is the SPI clock divider value (n 8); PCLK is derived from the
C.
Rev. 7 — 29 March 2011
DATA VALID
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
T
DATA VALID
SPICYC
LPC1759/58/56/54/52/51
t
SPIQV
Min
10
79.6
0.485
0
2
2
2
0
2
2
2
T
T
T
T
T
T
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
32-bit ARM Cortex-M3 microcontroller
T
t
t
SPICLKH
SPICYC
SPIDSU
5
+ 30
+ 5
+ 5
+ 35
+ 15
DATA VALID
DATA VALID
t
SPICLKL
t
SPIDH
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
0.515
-
-
-
-
-
-
-
-
t
002aad986
© NXP B.V. 2011. All rights reserved.
SPIOH
T
SPICYC
56 of 74
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns