NUC140VE3CN Nuvoton Technology Corporation of America, NUC140VE3CN Datasheet - Page 204

• Manufacturer Part Number: NUC140VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.6.6
I
Register
I2CON
Bits
[31:8]
[7]
[6]
[5]
[4]
[3]
2
C Control Register (I2CON)
Register Description
31
23
15
EI
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
I2C_BA+0x00
Descriptions
Reserved
EI
ENS1
STA
STO
SI
ENS1
30
22
14
6
R/W
R/W
Reserved
Enable Interrupt
1 = Enable I
0 = Disable I
I
1 = Enable
0 = Disable
Set to enable I
enables. The multi-function pin function of SDA and SCL must set to I
I
Setting STA to logic 1 to enter master mode, the I
repeat START condition to bus when the bus is free.
I
In master mode, setting STO to transmit a STOP condition to bus then I
will check the bus condition if a STOP condition is detected this bit will be cleared by
hardware automatically. In a slave mode, setting STO resets I
defined “not addressed” slave mode. This means it is NO LONGER in the slave
receiver mode to receive data from the master transmit device.
I
When a new I
hardware, and if bit EI (I2CON [7]) is set, the I
cleared by software. Clear SI is by writing 1 to this bit.
STA
2
2
2
2
C Controller Enable Bit
C START Control Bit
C STOP Control Bit
C Interrupt Flag
29
21
13
5
Description
I
2
C Control Register
2
2
C interrupt
C interrupt
2
STO
C state is present in the I2CSTATUS register, the SI flag is set by
2
28
20
12
C serial function controller. When ENS1=1 the I
4
- 204 -
Reserved
Reserved
Reserved
27
19
11
SI
3
Publication Release Date: June 14, 2011
AA
26
18
10
2
2
C interrupt is requested. SI must be
2
C hardware sends a START or
25
17
9
1
2
Reserved
C hardware to the
Revision V2.01
2
2
C serial function
C function first.
Reset Value
0x0000_0000
2
C hardware
24
16
8
0