NUC140VE3CN Nuvoton Technology Corporation of America, NUC140VE3CN Datasheet - Page 390

• Manufacturer Part Number: NUC140VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The data in the bit timing registers is the configuration input of the CAN protocol controller. The
Baud Rate Prescaler (configured by BRP) defines the length of the time quantum, the basic
time unit of the bit time; the Bit Timing Logic (configured by TSEG1, TSEG2, and SJW) defines
the number of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and
occasional synchronizations are controlled by the BTL (Bit Timing Logic) state machine, which is
evaluated once each time quantum. The rest of the CAN protocol controller, the BSP (Bit
Stream Processor) state machine is evaluated once each bit time, at the Sample Point.
The Shift Register sends the messages serially and parallelizes received messages. Its loading
and shifting is controlled by the BSP.
The BSP translates messages into frames and vice versa. It generates and discards the
enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code,
performs the error management, and decides which type of synchronization is to be used. It is
evaluated at the Sample Point and processes the sampled bus input bit. The time that is needed
to calculate the next bit to be sent after the Sample point (e.g. data bit, CRC bit, stuff bit, error
flag, or idle) is called the Information Processing Time (IPT).
The IPT is application specific but may not be longer than 2 t q ; the IPT for the C_CAN is 0 t q . Its
length is the lower limit of the programmed length of Phase_Seg2. In case of a synchronization,
Phase_Seg2 may be shortened to a value less than IPT, which does not affect bus timing.
APB Clock
APB Clock
Received_Data
Received_Data
Transmit_Data
Transmit_Data
NuMicro™ NUC130/NUC140 Technical Reference Manual
Baudrate_
Baudrate_
Prescaler
Prescaler
Figure 5-87 Structure of the CAN Core’s CAN Protocol Controller
Configuration (BRP)
Configuration (BRP)
Timing
Timing
Logic
Logic
Bit
Bit
Scaled_Clock (tq)
Scaled_Clock (tq)
Next_Data_Bit
Next_Data_Bit
Configuration (TSEG1, TSEG2, SJW)
Configuration (TSEG1, TSEG2, SJW)
Sample_Point
Sample_Point
Sample_Bit
Sample_Bit
Sync_Mode
Sync_Mode
Bit_to_send
Bit_to_send
Bus_Off
Bus_Off
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Control
Control
Stream
Stream
Processor
Processor
Shift-Register
Shift-Register
Publication Release Date: June 14, 2011
Bit
Bit
Control
Control
Status
Status
Received_Data_Bit
Received_Data_Bit
Send_Message
Send_Message
Received_Message
Received_Message
Revision V2.01