NUC140VE3CN Nuvoton Technology Corporation of America, NUC140VE3CN Datasheet - Page 387

• Manufacturer Part Number: NUC140VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

than the SJW, limiting the oscillator’s tolerance range.
The examples in Figure 5-85 show how the Phase Buffer Segments are used to compensate for
phase errors. There are three drawings of each two consecutive bit timings. The upper drawing
shows the synchronization on a “late” edge, the lower drawing shows the synchronization on an
“early” edge, and the middle drawing is the reference without synchronization.
In the first example an edge from recessive to dominant occurs at the end of Prop_Seg. The edge
is “late” since it occurs after the Sync_Seg. Reacting to the “late” edge, Phase_Seg1 is
lengthened so that the distance from the edge to the Sample Point is the same as it would have
been from the Sync_Seg to the Sample Point if no edge had occurred. The phase error of this
“late” edge is less than SJW, so it is fully compensated and the edge from dominant to recessive
at the end of the bit, which is one nominal bit time long, occurs in the Sync_Seg.
In the second example an edge from recessive to dominant occurs during Phase_Seg2. The edge
is “early” since it occurs before a Sync_Seg. Reacting to the “early” edge, Phase_Seg2 is
shortened and Sync_Seg is omitted, so that the distance from the edge to the Sample Point is the
same as it would have been from an Sync_Seg to the Sample Point if no edge had
occurred. As in the previous example, the magnitude of this “early” edge’s phase error is less than
SJW, so it is fully compensated.
The Phase Buffer Segments are lengthened or shortened temporarily only; at the next bit time, the
segments return to their nominal programmed values.
In these examples, the bit timing is seen from the point of view of the CAN implementation’s state
machine, where the bit time starts and ends at the Sample Points. The state machine omits
Sync_Seg when synchronising on an “early” edge because it cannot subsequently redefine that
time quantum of Phase_Seg2 where the edge occurs to be the Sync_Seg.
The examples in Figure 5-86 show how short dominant noise spikes are filtered by
synchronisations. In both examples the spike starts at the end of Prop_Seg and has the length of
(Prop_Seg + Phase_Seg1).
In the first example, the Synchronisation Jump Width is greater than or equal to the phase error of
the spike’s edge from recessive to dominant. Therefore the Sample Point is shifted after the end of
Rx-input
Rx-input
Rx-input
Rx-input
NuMicro™ NUC130/NUC140 Technical Reference Manual
Sync_Seg
Sync_Seg
Sync_Seg
Figure 5-85 Synchronization on “late” and “early” Edges
“Late Edge
“Late Edge
Sample-Point
Sample-Point
Sample-Point
Sample-Point
Prop_Seg
Prop_Seg
Prop_Seg
Sample-Point
Sample-Point
- 387 -
“early Edge
“early Edge
Publication Release Date: June 14, 2011
Phase_Seg1
Phase_Seg1
Phase_Seg1
Sample-Point
Sample-Point
Sample-Point
Sample-Point
Sample-Point
Sample-Point
Phase_Seg2
Phase_Seg2
Phase_Seg2
recessive
recessive
dominant
dominant
Revision V2.01
recessive
recessive
dominant
dominant