NUC130RE3CN Nuvoton Technology Corporation of America, NUC130RE3CN Datasheet - Page 293

• Manufacturer Part Number: NUC130RE3CN
• Description: IC MCU 32BIT 128KB FLASH 64LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130RE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.9.8
SPI Control and Status Register (SPI_CNTRL)
Register
SPI_CNTRL
Bits
[31:28]
[27]
[26]
[25]
[24]
[23]
[22]
VARCLK_EN
Register Description
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
SPIx_BA+0x00
Descriptions
Reserved
TX_FULL
TX_EMPTY
RX_FULL
RX_EMPTY
VARCLK_EN
TWOB
TWOB
30
22
14
6
SP_CYCLE
Reserved
TX_BIT_LEN
R/W
R/W
Reserved
Transmitted FIFO_FULL STATUS (read only)
1 = Indicates that the transmitted data buffer is full on the FIFO
0 = Indicates that the transmitted data buffer is not full
Transmitted FIFO_EMPTY STATUS (read only)
1 = Indicates that the transmitted data buffer is empty
0 = Indicates that the transmitted data buffer is not empty
Received FIFO_FULL STATUS (read only)
1 = Indicates that the receive data buffer is full on the FIFO
0 = Indicates that the receive data buffer is not full
Received FIFO_EMPTY STATUS (read only)
1 = Indicates that the receive data buffer is empty
0 = Indicates that the receive data buffer is not empty
Variable Clock Enable (Master Only)
1 = The serial clock output frequency is variable. The output frequency is decided by
0 = The serial clock output frequency is fixed and decided only by the value of
Note that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be
programmed as 0x10 (16-bit mode)
Two Bits Transfer Mode Active
FIFO
29
21
13
5
the value of VARCLK, DIVIDER, and DIVIDER2.
DIVIDER.
Description
Control and Status Register
28
20
12
4
- 293 -
REORDER
TX_FULL
CLKP
27
19
11
3
Publication Release Date: June 14, 2011
TX_EMPTY
TX_NEG
SLAVE
LSB
26
18
10
2
RX_FULL
RX_NEG
25
17
IE
9
1
TX_NUM
Revision V2.01
Reset Value
0x0500_0004
RX_EMPTY
GO_BUSY
24
16
IF
8
0