STM32F407IGT6 STMicroelectronics, STM32F407IGT6 Datasheet - Page 79

• Manufacturer Part Number: STM32F407IGT6
• Description: IC MCU 32BIT 1MB FLASH 176LQFP
• Manufacturer: STMicroelectronics

Specifications of STM32F407IGT6

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 168MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 140
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 24x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: ARM Cortex M4
• Processor Series: STM32F4
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 168 MHz
• Data Ram Size: 192 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 140
• Number Of Timers: 10
• Operating Supply Voltage: 1.7 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, I2C, I2S, SPI, UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11604

STM32F405xx, STM32F407xx
Table 31.
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
2. Guaranteed by design, not tested in production.
3. Maximum input PLL frequency is recommended for applications sensitive of long term jitter.
4. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
5. Based on characterization, not tested in production.
Table 32.
Jitter
I
I
f
f
f
t
DD(PLL)
DDA(PLL)
PLLI2S_IN
PLLI2S_OUT
VCO_OUT
LOCK
between PLL and PLLI2S.
Symbol
Symbol
(4)
(5)
(5)
Main PLL characteristics (continued)
PLLI2S (audio PLL) characteristics
Cycle-to-cycle jitter
Period Jitter
Main clock output (MCO) for
RMII Ethernet
Main clock output (MCO) for MII
Ethernet
Bit Time CAN jitter
Main clock output (MCO) for
RMMI Ethernet
PLL power consumption on VDD
PLL power consumption on
VDDA
PLLI2S input clock
PLLI2S multiplier output clock
PLLI2S VCO output
PLLI2S lock time
Parameter
Parameter
(2)
Doc ID 022152 Rev 1
VCO freq = 192 MHz
VCO freq = 432 MHz
System clock
120 MHz
Cycle to cycle at 50 MHz
on 1000 samples
Cycle to cycle at 25 MHz
on 1000 samples
Cycle to cycle at 1 MHz
on 1000 samples
Long term Jitter, PLL
input=6.25MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
(1)
Conditions
Conditions
peak
to
peak
peak
to
peak
RMS
RMS
0.15
0.45
0.30
0.55
Min
0.95
-
-
-
-
-
-
-
-
Min
192
100
75
-
(3)
Electrical characteristics
±150
±200
Typ
330
1.6
25
15
32
40
-
-
Typ
1
-
-
-
-
Max
0.40
0.75
0.40
0.85
2.0
Max
216
432
200
300
-
-
-
-
-
-
-
-
(4)
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Unit
mA
mA
MHz
MHz
MHz
Unit
ps
ns
µs