C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 114

• Manufacturer Part Number: C8051F700-GQR
• Description: MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-GQR

• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F70x
• Maximum Speed: 25 MHz
• Ram Size: 512 Byte
• Program Memory Size: 15 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 54
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 16-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F70x/71x
SFR Definition 18.2. EMI0CF: External Memory Configuration
SFR Address = 0xC7; SFR Page = F
114
Name
Reset
7:5
3:2
1:0
Bit
Type
4
Bit
EALE[1:0] ALE Pulse-Width Select Bits.
EMD[1:0]
Unused
Name
EMD2
7
0
Read = 000b; Write = Don’t Care.
EMIF Multiplex Mode Select Bit.
0: EMIF operates in multiplexed address/data mode
1: EMIF operates in non-multiplexed mode (separate address and data pins)
EMIF Operating Mode Select Bits.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
on-chip memory space
01: Split Mode without Bank Select: Accesses below the 256 B boundary are directed
on-chip. Accesses above the 256 B boundary are directed off-chip. 8-bit off-chip MOVX
operations use current contents of the Address high port latches to resolve the upper
address byte. To access off chip space, EMI0CN must be set to a page that is not con-
tained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 256 B boundary are directed on-
chip. Accesses above the 256 B boundary are directed off-chip. 8-bit off-chip MOVX
operations uses the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to
the CPU.
These bits only have an effect when EMD2 = 0.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
R
6
0
5
0
EMD2
Rev. 1.0
4
0
Function
3
0
EMD[1:0]
R/W
2
0
1
1
EALE[1:0]
0
1