C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 250
C8051F700-GQR
Manufacturer Part Number
C8051F700-GQR
Description
MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F700DK.pdf
(306 pages)
Specifications of C8051F700-GQR
Package
64TQFP
Device Core
8051
Family Name
C8051F70x
Maximum Speed
25 MHz
Ram Size
512 Byte
Program Memory Size
15 KB
Operating Supply Voltage
1.8|3 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
54
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
16-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
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C8051F70x/71x
SFR Definition 31.3. SPI0CKR: SPI0 Clock Rate
SFR Address = 0xA2; SFR Page = F
SFR Definition 31.4. SPI0DAT: SPI0 Data
SFR Address = 0xA3; SFR Page = 0
250
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
SPI0DAT[7:0] SPI0 Transmit and Receive Data.
SCR[7:0]
Name
Name
7
0
7
0
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
f
f
f
SCK
SCK
SCK
6
0
6
0
=
=
=
---------------------------------------------------------- -
2
------------------------- -
2
200kHz
2000000
5
0
5
0
SPI0CKR[7:0]
4
+
SYSCLK
1
Rev. 1.0
4
0
4
SPI0DAT[7:0]
0
SCR[7:0]
R/W
R/W
+
1
Function
Function
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
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