DS21352L+ Maxim Integrated Products, DS21352L+ Datasheet - Page 23

• Manufacturer Part Number: DS21352L+
• Description: IC TXRX T1 1-CHIP 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21352L+

• Function: Single-Chip Transceiver
• Interface: HDLC, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

4.1.4 JTAG TEST ACCESS PORT PINS
Signal Name:
Signal Description:
Signal Type:
If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally.
If FMS = 0: JTAG functionality is available and JTRST is pulled up internally by a 10kΩ resistor.
If FMS = 0 and boundary scan is not used, this pin should be held low. This signal is used to asynchronously reset the test
access port controller. The device operates as a T1/E1 transceiver if JTRST is pulled low.
Signal Name:
Signal Description:
Signal Type:
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1
states. This pin has a 10k pull up resistor.
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pull up resistor.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left
unconnected.
4.1.5 INTERLEAVE BUS OPERATION PINS
Signal Name:
Signal Description:
Signal Type:
A rising edge on this pin causes RSER and RSIG to come out of high Z state and TSER and TSIG to start sampling on the next
rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of data. This pin has a 10k pull up resistor.
Signal Name:
Signal Description:
Signal Type:
An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER
and RSIG.
JTRST
IEEE 1149.1 Test Reset
Input
JTMS
IEEE 1149.1 Test Mode Select
Input
JTCLK
IEEE 1149.1 Test Clock Signal
Input
JTDI
IEEE 1149.1 Test Data Input
Input
JTDO
IEEE 1149.1 Test Data Output
Output
CI
Carry In
Input
CO
Carry Out
Output
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