IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 28

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

3.2.3
according to the amplitude of the input signals. The input signal is sliced
at 50% of the peak value.
3.2.4
from the received data. It is accomplished by an integrated Digital Phase
Locked Loop (DPLL). The recovered clock tracks the jitter in the data
output from the Slicer and keeps the phase relationship between data
and clock during the absence of the incoming pulse.
REFB pins to output any of the 17 recovered line clocks. Refer to
Section 3.6 Clock Inputs and Outputs for details.
3.2.5
Single Rail NRZ Format mode. When the receive system interface is in
other modes, the Decoder is bypassed automatically. (Refer to
Section 3.2.6 Receive System Interface for the description of the receive
system interface).
code rule. In E1 mode, the received signal is decoded by AMI or HDB3
line code rule. The line code rule is selected by the R_CODE bit (b2,
RCF1,...).
3.2.6
Single Rail NRZ Format mode, Dual Rail NRZ Format mode, Dual Rail
RZ Format mode and Dual Rail Sliced mode, as selected by the
R_MD[1:0] bits (b1~0, RCF1).
output on RCLKn, the receive system interface is in Single Rail NRZ
Format mode. In this mode, the data is decoded and updated on the
active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode) or
2.048 MHz (in E1 mode) clock. The Receive Multiplex Function (RMFn)
signal is updated on the active edge of RCLKn and can be selected to
indicate PRBS/ARB, LAIS, LEXZ, LBPV, LEXZ + LBPV, LLOS, output
Functional Description
IDT82P2816
The Slicer is used to generate a standard amplitude mark or a space
The Rx Clock & Data Recovery is used to recover the clock signal
Note that the IDT82P2816 also provides programmable REFA and
The Decoder is used only when the receive system interface is in
In T1/J1 mode, the received signal is decoded by AMI or B8ZS line
The received data can be output to the system side in four modes:
If data is output on RDn in NRZ format and the recovered clock is
SLICER
R
DECODER
RECEIVE SYSTEM INTERFACE
X
CLOCK & DATA RECOVERY
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
28
recovered clock (RCLK) or XOR output of positive and negative sliced
data. Refer to Section 3.5.7.1 RMFn Indication for the description of
RMFn.
ered clock is output on RCLKn, the receive system interface is in Dual
Rail NRZ Format mode. In this mode, the data is un-decoded and
updated on the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) clock.
clock is output on RCLKn, the receive system interface is in Dual Rail
RZ Format mode. In this mode, the data is un-decoded and updated on
the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode)
or 2.048 MHz (in E1 mode) clock.
passing through the Slicer, the receive system interface is in Dual Rail
Sliced mode. In this mode, the data is raw sliced and un-decoded.
RMFn can be selected to indicate PRBS/ARB, LAIS, LEXZ, LBPV, LEXZ
+ LBPV, LLOS, output recovered clock (RCLK) or XOR output of positive
and negative sliced data. Refer to Chapter 3.5.7.1 RMFn Indication for
the description of RMFn.
system interface.
Table-3 Multiplex Pin Used in Receive System Interface
Single Rail NRZ Format
Note:
1. The active level on RDn, RDPn and RDNn is selected by the RD_INV bit (b3,
RCF1,...).
2. RMFn is always active high.
3. The active edge of RCLKn is selected by the RCK_ES bit (b4, RCF1,...).
Dual Rail NRZ Format
Dual Rail RZ Format
If data is output on RDPn and RDNn in NRZ format and the recov-
If data is output on RDPn and RDNn in RZ format and the recovered
If data is output on RDPn and RDNn in RZ format directly after
Table-3 summarizes the multiplex pin used in different receive
Receive System
Dual Rail Sliced
Interface
RDn / RDPn
RDPn
RDPn
RDPn
Multiplex Pin Used On Receive System
RDn
1
1
1
1
RDNn / RMFn
Interface
RMFn
RDNn
RDNn
RDNn
2
1
1
1
February 6, 2009
RCLKn /
RCLKn
RCLKn
RCLKn
RMFn
RMFn
2
3
3
3