IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 56

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

3.6
different frequencies.
3.6.1
the clocks required by internal circuits and CLKT1/CLKE1 outputs.
MCLK should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm
(in E1 mode) accuracy. The clock frequency of MCLK is 1.544/2.048 X N
MHz (1 ≤ N ≤ 8, N is an integer number), as determined by
MCKSEL[3:0]. Refer to Chapter 2 Pin Description for details.
Functional Description
IDT82P2816
The IDT82P2816 provides two kinds of clock outputs:
• Free running clock outputs on CLKT1 and CLKE1
• Receiver clock outputs on REFA and REFB
A Frequency Synthesizer is also available to scale REFA to 8
The following Clock Inputs are provided:
• MCLK as programmable reference timing for the IDT82P2816.
• CLKA and CLKB as optional input clock source for REFA and
An internal clock generator uses MCLK as reference to generate all
- selected from any of the 17 recovered line clocks
- driven by MCLK (free running)
- driven by external CLKA/CLKB input
REFB respectively
CLOCK INPUTS AND OUTPUTS
FREE RUNNING CLOCK OUTPUTS ON CLKT1/CLKE1
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
56
MCLK). The output of CLKT1 is determined by the CLKT1_EN bit (b1,
CLKG) and the CLKT1 bit (b0, CLKG). Refer to Table-23. The output of
CLKE1 is determined by the CLKE1_EN bit (b3, CLKG) and the CLKE1
bit (b2, CLKG). Refer to Table-24.
Table-23 Clock Output on CLKT1
Table-24 Clock Output on CLKE1
The outputs on CLKT1 and CLKE1 are free running (locking to
CLKE1_EN
CLKT1_EN
0
1
0
1
Control Bits
Control Bits
(don’t-care)
(don’t-care)
CLKT1
CLKE1
0
1
0
1
Clock Output On CLKT1
Clock Output On CLKE1
1.544 KHz
2.048 KHz
February 6, 2009
High-Z
High-Z
8 KHz
8 KHz