IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 78

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

Programming Information
IDT82P2816
2 - 0
3
FREQ[2:0]
FREE
This bit is valid only when the selected clock source for REFA passes the internal Frequency Synthesizer
In normal operation:
0: Output the clock which is locked to the selected clock source and the frequency is programmed in the FREQ[2:0] bits (b2~0,
REFCF). (default)
1: Output free running clock which is locked to MCLK and the frequency is programmed in the FREQ[2:0] bits (b2~0, REFCF).
When the selected clock source is lost, this bit, together with the FS_BYPAS bit (b4, REFCF) and the REFH bit (b5, REFCF),
controls the output on REFA:
These bits are valid only when the Frequency Synthesizer on REFA is enabled. These bits determine the output clock frequency.
FREQ[2:0]
Recovered clock of
one of the 17 chan-
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Selected Clock
Source
CLKA
nels.
1.544 MHz if the selected clock source is 1.544 MHz; or
2.048 MHz if the selected clock source is 2.048 MHz
Frequency Synthesizer uses RCLKn or CLKA as
Output when FS_BYPAS=0, FREE=0 and the
FS_BYPA
S
0
1
0
1
reference clock
32.768 MHz
4.096 MHz
8.192 MHz
19.44 MHz
Reserved
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
64 kHz
8 kHz
(don’t-
FREE
78
care)
0
1
0
1
(don’t-care)
(don’t-
(don’t-
REFH
care)
care)
0
1
0
1
High level.
Free running clock, whose frequency is programmed
in the FREQ[2:0] bits (b2~0, REFCF).
High level.
Free running clock, whose frequency is programmed
in the FREQ[2:0] bits (b2~0, REFCF).
High level.
Free running clock, whose frequency is programmed
in the FREQ[2:0] bits (b2~0, REFCF).
Free running clock, whose frequency is 1.544 MHz in
T1 mode or 2.048 MHz in E1 mode.
High level.
(the Frequency Synthesizer is free running)
Output when FS_BYPAS=0 and FREE=1
Output On REFA
32.768 MHz
4.096 MHz
8.192 MHz
19.44 MHz
64 kHz
8 kHz
-
-
February 6, 2009