SI3019-F-FT Silicon Laboratories Inc, SI3019-F-FT Datasheet - Page 100

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SI3019-F-FT

Manufacturer Part Number
SI3019-F-FT
Description
IC VOICE DAA GCI/PCM/SPI 16TSSOP
Manufacturer
Silicon Laboratories Inc
Type
Chipsetr
Datasheets

Specifications of SI3019-F-FT

Package / Case
16-TSSOP
Function
Data Access Arrangement (DAA)
Interface
GCI, PCM, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Product
Modem Chip
Supply Voltage (min)
3 V
Supply Current
8.5 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Si3050
8. Pin Descriptions: Si3018/19
100
Pin #
10
12
13
11
1
2
3
4
5
6
7
8
9
Pin Name
VREG2
VREG
RNG1
RNG2
DCT
C1B
C2B
QE2
QE
QB
RX
SC
IB
Transistor Emitter.
Connects to the emitter of Q3.
DC Termination.
Provides dc termination to the telephone network.
Receive Input.
Serves as the receive side input from the telephone network.
Internal Bias.
Provides a bias voltage to the device.
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1. Used to communicate with the
system-side device.
Isolation Capacitor 2B.
Connects to one side of isolation capacitor C2. Used to communicate with the
system-side device.
Voltage Regulator.
Connects to an external capacitor to provide bypassing for an internal power supply.
Ring 1.
Connects through a resistor to the TIP lead of the telephone line. Provides the ring and caller
ID signals to the DAA.
Ring 2.
Connects through a resistor to the RING lead of the telephone line. Provides the ring and
caller ID signals to the DAA.
Voltage Regulator 2.
Connects to an external capacitor to provide bypassing for an internal power supply.
SC Connection.
Enables external transistor network. Should be tied through a 0 Ω resistor to I
Transistor Emitter 2.
Connects to the emitter of Q4.
Transistor Base.
Connects to the base of transistor Q4.
VREG
RNG1
DCT
C1B
C2B
QE
RX
IB
1
2
3
4
5
6
7
8
Rev. 1.2
16
15
14
13
12
11
10
9
Description
DCT2
IGND
DCT3
QB
QE2
SC
VREG2
RNG2
GND
.

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