SI3019-F-FT Silicon Laboratories Inc, SI3019-F-FT Datasheet - Page 24

• Manufacturer Part Number: SI3019-F-FT
• Description: IC VOICE DAA GCI/PCM/SPI 16TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Chipsetr

Specifications of SI3019-F-FT

• Package / Case: 16-TSSOP
• Function: Data Access Arrangement (DAA)
• Interface: GCI, PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Product: Modem Chip
• Supply Voltage (min): 3 V
• Supply Current: 8.5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si3050
5.2. Power Supplies
The Si3050 operates from a 3.3 V power supply. The
Si3050 input pins can only accept 3.3 V CMOS signal
levels. If support of 5 V signal levels is necessary, a
level shifter is required. The Si3018/19 derives its power
from two sources: the Si3050 and the telephone line.
The Si3050 supplies power over the patented isolation
capacitor link between the two devices, allowing the
Si3019 to communicate with the Si3050 while on-hook
and perform other on-hook functions, such as line
voltage monitoring. When off-hook, the Si3018/19 also
derives power from the line current supplied from the
telephone line. This feature is exclusive to DAAs from
Silicon Labs and allows the most cost-effective
implementation for a DAA while still maintaining robust
performance over all line conditions.
5.3. Initialization
Each time the Si3050 is powered up, assert the RESET
pin. When the RESET pin is deasserted, the registers
have default values to guarantee the line-side device
(Si3018/19) is powered down without the possibility of
loading the line (i.e., off-hook). An example initialization
procedure follows:
1. Power up and de-assert RESET.
2. Wait until the PLL is locked. This time is less than
3. Enable PCM (Register 33) or GCI (Register 42)
4. Set the desired line interface parameters (i.e.,
5. Set the FULL (or FULL2) + IIRE bits as required.
6. Write a 0x00 into Register 6 to power up the
When this procedure is complete, the Si3018/19 is
ready for ring detection and off-hook operation.
5.4. Isolation Barrier
The Si3050 achieves an isolation barrier through
low-cost, high-voltage capacitors in conjunction with
Silicon
techniques.
eliminates
mismatches, common mode interference, or noise
coupling. As shown in the "2. Typical Application
Schematic" on page 17, the C1, C2, C8, and C9
capacitors isolate the Si3050 (system-side) from the
Si3018/19 (line-side). Transmit, receive, control, ring
detect, and caller ID data are passed across this barrier.
24
1 ms from the application of PCLK.
mode.
DCV[1:0], MINI[1:0], ILIM, DCR, ACIM[3:0], OHS,
RT, RZ, TGA2, and TXG2[3:0]) shown in Table 13 on
page 21.
line-side device (Si3018/19).
Laboratories’
signal
Differential
degradation
patented
capacitive
signal
from
communication
processing
capacitor
Rev. 1.2
The communications link is disabled by default. To
enable it, the PDL bit (Register 6, bit 4) must be
cleared. No communication between the Si3050 and
Si3018/19 can occur until this bit is cleared. Allow the
PLL to lock to the PCLK and FSYNC input signals
before clearing the PDL bit.
5.5. Power Management
The Si3050 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
The power management modes are controlled by the
PDN and PDL bits (Register 6).
On powerup, or following a reset, the Si3050 is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The Si3050 is operational, except for the
communications link. No communication between the
Si3050 and line-side device (Si3018/19) can occur
during reset operation. Bits associated with the line-side
device are invalid in this mode.
In typical applications, the DAA will predominantly be
operated in normal mode. In normal mode, the PDL and
PDN bits are cleared. The DAA is operational and the
communications link passes information between the
Si3050 and the Si3018 or Si3019.
The Si3050 supports a low-power sleep mode that
supports ring validation and wake-up-on-ring features.
To enable the sleep mode, the PDN bit must be set.
When the Si3050 is in sleep mode, the PCLK signal
must remain active. In low-power sleep mode, the
Si3050 is non-functional except for the communications
link and the RGDT signal. To take the Si3050 out of
sleep mode, pulse the reset pin (RESET) low.
In summary, the powerdown/up sequence for sleep
mode is as follows:
1. Ensure the PDL bit (Register 6, bit 4) is cleared.
2. Set the PDN bit (Register 6, bit 3).
3. The device is now in sleep mode. PCLK must remain
4. To exit sleep mode, reset the Si3050 by pulsing the
5. Program registers to desired settings.
The Si3050 also supports an additional Powerdown
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) bits are set, the chipset enters a
complete powerdown mode and draws negligible
current (deep sleep mode). In this mode, the Si3050 is
non-functional. The RGDT pin does not function and the
Si3050 will not detect a ring. Normal operation can be
restored using the same process for taking the Si3050
out of sleep mode.
active.
RESET pin.