SI3220-KQ Silicon Laboratories Inc, SI3220-KQ Datasheet - Page 53

• Manufacturer Part Number: SI3220-KQ
• Description: IC SLIC/CODEC DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3220-KQ

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 65mA
• Power (watts): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Product: Telecom
• Supply Voltage (min): 3.13 V
• Supply Current: 22 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The user must enter the value of R
software so the equalizer block can compensate for
additional series impedance. (See Figure 11 on page
22.) Figure 34 illustrates the simplified two-wire
impedance
resistors, where Z
specific geographical region. The Dual ProSLIC devices
can accomodate up to 50 Ω of series protection
impedance per leg. The Dual ProSLIC devices load a
600 Ω default setting into the RS register if the user
does not define the impedance setting, which assumes
there is no additional series protection resistance.
The ac impedance generation scheme is comprised of
analog and DSP-based coefficients. To turn off the
analog coefficients (RS, ZP, and ZZ bits in the ZRS and
ZZ registers), the user can simply set the ZSDIS bit of
the ZZ register to 0. To turn off the DSP coefficients
(ZA1H1 through ZB3LO registers), each register must
be loaded with 0x00.
Figure 34. Two-Wire Impedance Simplified
Z
L
Z
R
protection devices
R
impedance
R
synthesized impedance
RING
circuit
T
TIP
PROT
S
P
||C
is the series portion of the synthesized
L
P
R
R
is the actual line impedance for the
PROT
PROT
is the series resistance caused by
is the parallel portion of the
including
Circuit
external
PROT
ProSLIC
Dual
protection
Preliminary Rev. 0.91
into the
Transhybrid Balance Filter
The Dual ProSLIC devices provide a transhybrid
balance function via a digitally programmable balance
filter block. (See “H” block in Figure 11 on page 22.) The
Dual ProSLIC devices implement a 8-tap FIR filter and a
second order IIR filter, both running at a 16 kHz sample
rate. These two filters combine to form a digital replica
of the reflected signal (echo) from the transmit path
inputs. The user can filter settings on a per-line basis by
loading the desired impedance cancellation coefficients
into the appropriate registers. The Si322X Coefficient
Generator software interface is provided for calculating
the appropriate coefficients for the FIR and IIR filter
blocks.
The transhybrid balance filters can be disabled to
implement loopback diagnostic modes. To disable the
transhybrid balance filter (zero cancellation), set the
HYBDIS bit in the DIGCON register to 1. With the hybrid
balance cancellation scheme disabled, the user can
accurately measure the full transmit path signal to
measure the two-wire return loss.
Note: The user must enter values into each register location
Tone Generators
Dual ProSLIC devices have two digital tone generators
that allow a wide variety of single or dual tone frequency
and amplitude combinations that spare the user the
effort of generating the required POTS signaling tones
on the PCM highway. DTMF, FSK (caller ID), call
progress, and other tones can all be generated on-chip.
The tones are sent to the receive or transmit paths.
(See Figure 11 on page 22.)
Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 35. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected for flexibility in creating audio signals.
Control and status register bits are placed in the figure
to indicate their association with the tone generator
architecture. The register set for tone generation is
summarized in Table 31 on page 55.
to ensure correct operation when the hybrid balance
block is enabled.
Si3220/Si3225
53