SI3220-KQ Silicon Laboratories Inc, SI3220-KQ Datasheet - Page 62

• Manufacturer Part Number: SI3220-KQ
• Description: IC SLIC/CODEC DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3220-KQ

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 65mA
• Power (watts): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Product: Telecom
• Supply Voltage (min): 3.13 V
• Supply Current: 22 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Si3220/Si3225
Interrupt Logic
The Dual ProSLIC devices are capable of generating
interrupts for the following events:
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The interface to the interrupt logic consists of six
registers. Three interrupt status registers (IRQ0–IRQ3)
contain 1 bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1–IRQEN3) also contain 1 bit for each interrupt
function. For interrupt mask registers, the bits are active
high. Refer to the appropriate functional description text
for operational details of the interrupt functions.
When a resource reaches an interrupt condition, it
signals an interrupt to the interrupt control block. The
interrupt control block sets the associated bit in the
interrupt status register if the mask bit for that interrupt
is set. The INT pin is a NOR of the bits of the interrupt
status registers. Therefore, if a bit in the interrupt status
registers is asserted, IRQ asserts low. Upon receiving
the interrupt, the interrupt handler should read interrupt
status registers to determine which resource requests
service. All interrupt bits in the interrupt status registers
IRQ0–IRQ3 are cleared following a register read
operation. If the interrupt status registers are non-0, the
INT pin remains asserted.
SPI Control Interface
The control interface to the Dual ProSLIC devices is a
4-wire interface modeled after micro-controller and
serial peripheral devices. The interface consists of a
clock (SCLK), chip select (CS), serial data input (SDI),
and serial data output (SDO). In addition, the Dual
ProSLIC devices include a serial data through output
(SDI_THRU) to support a daisy-chain operation of up to
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Loop current/ring ground detected.
Ring trip detected.
Ground Key detected.
Power alarm.
DTMF digit detected.
Active timer 1 expired.
Inactive timer 1 expired.
Active timer 2 expired.
Inactive timer 2 expired.
Ringing active timer expired.
Ringing inactive timer expired.
Pulse metering active timer expired.
Pulse metering inactive timer expired.
RAM address access complete.
Receive path modem tone detected.
Transmit path modem tone detected.
Preliminary Rev. 0.91
eight devices (up to sixteen channels). The device
operates with both 8-bit and 16-bit SPI controllers. Each
SPI operation consists of a control byte, an address
byte (of which only the seven LSBs are used internally),
and either one or two data bytes depending on the width
of the controller and whether the access is to an 8-bit
register or 16-bit RAM address.
transmitted MSB first.
There are variations of usage on this four-wire interface
as follows:
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Continuous clocking . During continuous clocking,
the data transfers are controlled by the assertion of
the CS pin. CS must be asserted before the falling
edge of SCLK on which the first bit of data is
expected during a read cycle, and must remain low
for the duration of the 8-bit transfer (command/
address or data), going high after the last rising of
SCLK after the transfer.
Clock during transfer only . In this mode, only the
clock is cycling during the actual byte transfers. Each
byte transfer will consist of eight clock cycles in a
return to “1” format.
SDI/SDO wired operation . Independent of the
clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is capable of tri-stating its output during the
data byte transfer of a read operation.
Soft reset . The SPI state machine resets whenever
CS asserts during an operation on an SCLK cycle
that is not a multiple of eight. This is a mechanism
for the controller to force the state machine to a
known state when the controller and the device are
out of synchronization.
Bytes are always