DS2155L Maxim Integrated Products, DS2155L Datasheet - Page 113

• Manufacturer Part Number: DS2155L
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2155L

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

DS2155
22.
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1
ONLY)
When operated in the E1 mode, the DS2155 provides three methods for accessing the Sa and the Si bits.
The first method involves a hardware scheme that uses the RLINK/RLCLK and TLINK/TLCLK pins
(Section 22.1). The second method involves using the internal RAF/RNAF and TAF/TNAF registers
(Section 22.2). The third method, which is covered in Section 22.3, involves an expanded version of the
second method.
22.1 Method 1: Hardware Scheme
On the receive side, all of the received data is reported at the RLINK pin. Using the E1RCR2 register, the
user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create
a clock that can be used to capture the needed Sa bits. If RSYNC is programmed to output a frame
boundary, it identifies the Si bits.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (Section
22.2) or externally from the TLINK pin. Using the E1TCR2 register, the framer can be programmed to
source any combination of the Sa bits from the TLINK pin. Si bits can be sampled through the TSER pin
if by setting E1TCR1.4 = 0.
22.2 Method 2: Internal Register Scheme Based on Double-Frame
On the receive side, the RAF and RNAF registers always report the data as it received in the Sa and Si bit
locations. The RAF and RNAF registers are updated on align-frame boundaries. The setting of the receive
align frame bit in Status Register 4 (SR4.0) indicates that the contents of the RAF and RNAF have been
updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers. The host has
250µs to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the transmit
align frame bit in Status Register 4 (SR4.3). The host can use the SR4.3 bit to know when to update the
TAF and TNAF registers. It has 250µs to update the data or else the old data is retransmitted. If the TAF
and TNAF registers are only being used to source the align frame and nonalign frame-sync
patterns, then the host need only write once to these registers. Data in the Si bit position is
overwritten if either the framer is (1) programmed to source the Si bits from the TSER pin, (2) in the
CRC4 mode, or (3) has automatic E-bit insertion enabled. Data in the Sa bit position is overwritten if any
of the E1TCR2.3 to E1TCR2.7 bits are set to 1.
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