DS2155L Maxim Integrated Products, DS2155L Datasheet - Page 54

IC TXRX T1/E1/J1 1-CHIP 100-LQFP

DS2155L

Manufacturer Part Number
DS2155L
Description
IC TXRX T1/E1/J1 1-CHIP 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheets

Specifications of DS2155L

Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-

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Table 9-A. T1 Alarm Criteria
Blue Alarm (AIS)
(Note 1)
Yellow Alarm (RAI)
D4 Bit 2 Mode
(T1RCR2.0 = 0)
D4 12th F-Bit Mode
(T1RCR2.0 = 1; this mode is also
referred to as the “Japanese Yellow
Alarm”)
ESF Mode
Red Alarm (LRCL)
(Also referred to as loss of signal)
Note 1: The definition of Blue Alarm (or AIS) is an unframed all-ones signal. Blue Alarm detectors should be able to operate properly in the
Note 2: ANSI specifications use a different nomenclature than the DS2155 does. The following terms are equivalent:
presence of a 10E-3 error rate and they should not falsely trigger on a framed all-1s signal. Blue Alarm criteria in the DS2155 has been
set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
RBL = AIS
RCL = LOS
RLOS = LOF
RYEL = RAI
ALARM
When over a 3ms window, five or
fewer 0s are received
When bit 2 of 256 consecutive
channels is set to 0 for at least 254
occurrences
When the 12th framing bit is set to 1
for two consecutive occurrences
When 16 consecutive patterns of
00FF appear in the FDL
When 192 consecutive 0s are
received
SET CRITERIA
54 of 238
When over a 3ms window, six or
more 0s are received
When bit 2 of 256 consecutive
channels is set to 0 for fewer than
254 occurrences
When the 12th framing bit is set to
0 for two consecutive occurrences
When 14 or fewer patterns of 00FF
hex out of 16 possible appear in the
FDL
When 14 or more 1s out of 112
possible bit positions are received
CLEAR CRITERIA
DS2155

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