DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 114

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

Table 10-34. Recommended Transformers
Note: Table subject to change. Industrial temperature range and multiport transformers are also available. Contact the manufacturers for details
at
10.12.5.2 Optional Preamp
The receiver can be used in monitoring applications, which typically have series resistors with a resistive loss of
approximately 20dB. When the PORT.CR2.RMON bit is high, the receiver compensates for this resistive loss by
applying flat gain to the incoming signal before sending the signal to the AGC/equalizer block.
10.12.5.3 Automatic Gain Control (AGC) and Adaptive Equalizer
The AGC circuitry applies flat (frequency independent) gain to the incoming signal to compensate for flat losses in
the transmission channel and variations in transmission power. Since the incoming signal also experiences
frequency-dependent losses as it passes through the coaxial cable, the adaptive equalizer circuitry applies
frequency-dependent gain to offset line losses and restore the signal. The AGC/equalizer circuitry automatically
adapts to coaxial cable losses from 0 to 15dB, which translates into 0 to 380 meters (DS3) or 0 to 440 meters (E3)
of coaxial cable (AT&T 734A or equivalent). The AGC and the equalizer work simultaneously but independently to
supply a signal of nominal amplitude and pulse shape to the clock and data recovery block. The AGC/equalizer
block automatically handles direct (0 meters) monitoring of the transmitter output signal.
10.12.5.4 Clock and Data Recovery (CDR)
The CDR block takes the amplified, equalized signal from the AGC/equalizer block and produces a separate clock,
positive data, and negative data signals. The CDR requires a master clock. This clock is derived from CLKA,
CLKB, or CLKC depending on the CLAD configuration (DS3, E3). If, however, there is no clock source on CLKA,
CLKB, or CLKC the CDR block will automatically switch to TCLKIn to use as its master clock.
The receive clock is locked using a clock recovery PLL. The status of the PLL lock is indicated in the RLOL
(PORT.SR) status bit. The receive loss-of-lock status bit (RLOL) is set when the difference between the recovered
clock frequency and the master clock frequency is greater than 7900ppm and cleared when the difference is less
than 7700ppm. A change of state of the PORT.SR.RLOL status bit can cause an interrupt on the INT pin if enabled
to do so by the PORT.SRIE.RLOLIE interrupt-enable bit. Note that if the master clock is not present, or the master
clock is high and TCLK is not present, RLOL is not set.
10.12.5.5 Loss-of-Signal (LOS) Detector
The receiver contains analog and digital LOS detectors. The analog LOS detector resides in the AGC/equalizer
block. If the incoming signal level is less than a signal level approximately 24dB below nominal, analog LOS
(ALOS) is declared. The ALOS signal cannot be directly examined, but when ALOS occurs the AGC/equalizer
mutes the recovered data, forcing all zeros out of the data recovery circuitry and causing digital LOS (DLOS).
DLOS is determined by the Line Decoder block (see
ALOS clears when the incoming signal level is greater than or equal to a signal level approximately 18dB below
nominal.
Pulse Engineering
Pulse Engineering
Halo Electronics
Halo Electronics
MANUFACTURER
www.pulseeng.com
and www.haloelectronics.com.
PE-65968
PE-65969
0206NS
0206NE
PART
TG07-
TD07-
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
RANGE
TEMP
10.10.6)
114
PIN-PACKAGE/
SCHEMATIC
6 Thru-Hole
LS-1/C
LC-1/C
SMD/B
6 SMT
6 SMT
and indicated by the LOS status bit (LINE.RSR.LOS).
DIP/B
6 DIP
(µH) (min)
PRIMARY
OCL
19
19
19
19
(max)
(µH)
0.06
0.06
0.06
0.06
L
L
BANDWIDTH
0.250 to 500
0.250 to 500
0.250 to 500
0.250 to 500
75Ω (MHz)