DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 31

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

PIN NAME
TCLKOn /
TGCLKn
TSOFIn
TCLKIn
TSERn
TYPE
O
I
I
I
Transmit Line Clock Input
TCLKIn: This clock is typically used for the reference clock for the TSOFIn, TSERn, and
TSOFOn / TDENn signals but can also be used as the reference for the TPOSn / TDATn and
TNEGn signals. This clock is not used when the part is in loop time mode or the CLAD clocks
are used as the transmit clock source. (PORT.CR3.CLADC)
This input signal can be inverted.
o
o
Transmit Start Of Frame Input
See
TSOFIn: This signal can be used to align the start of the DS3 or E3 frames on the TSERn pin to
an external signal. In SCT modes, the TSOFIn signal can be used to align the start of frame
signal position on the TSERn/TOHn
Pin to the rising edge of a signal on this pin. The signal edge does not need to occur on every
frame and can be tied high or low. The signal is sampled on the positive clock edge of the
referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling
edge of the clock. The signal is typically referenced to the TCLKIn transmit clock input pins, but
it can be referenced to the TLCLKn, TCLKOn, RCLKOn and RLCLKn clock pins.
This signal can be inverted.
Transmit Serial Data
TSERn: When the port framer is configured for either the DS3 or E3 SCT modes, this pin is
used as the source of the DS3/E3 payload data. When the port is configured for a clear channel
mode, this pin is used as the source of the DS3/E3 data signal. The signal is sampled on the
positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it
is sampled on the falling edge of the clock. The signal is typically referenced to the TCLKIn
transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn / TGCLKn, RCLKOn
and RLCLKn clock pins
This signal can be inverted.
o
o
Transmit Clock Output / Gapped Clock
See
TCLKOn: When the port is configured for unframed SCT or framed SCT modes and TCLKOn is
selected, this clock output is enabled. This clock is the same clock as the internal framer
transmit clock. This clock is typically used for the reference clock for the TSOFIn, TSERn, and
TSOFOn / TDENn signals but can also be used as the reference for the TPOSn / TDATn and
TNEGn signals.
This signal can be inverted.
o
o
TGCLKn: When the port is configured for framed DS3/E3 mode and TGCLKn is selected, this
gated output clock is enabled. This gapped clock is the same clock as the internal framer
transmit clock and is gated by TDENn. This clock is typically used for the reference clock for the
TSERn signal.
This signal can be inverted.
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
Table 10-20.
Table 10-22.
DS3/E3 SERIAL DATA OVERHEAD INTERFACE
31
PIN DESCRIPTION