DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 58

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

Table 10-7. Transmit Framer Pin Signal Timing Source Select
10.2.3.3 Receive Line Interface Pin Timing Source Selection
(RPOSn/RDATn, RNEGn/RLCVn)
The receive line interface signal pin group must clocked in with the RLCLK clock input pin. When the LIU is
enabled, the receive line interface pins are not used so there is no valid clock reference.
Table 10-8. Receive Line Interface Pin Signal Timing Source Select
10.2.3.4 Receiver Framer Pin Timing Source Selection
(RSERn, RSOFOn/RDENn)
The receive framer signal pin group has the same functional timing clock source as the RCLKOn pin described in
Table
Other clock pins can be used for the external timing. The RCLKOn receive clock output pin is always a valid output
clock for external logic to use for these signals when PORT.CR3.RFTS=0.
The receive framer timing select bit (RFTS) is used to select input or output clock pin timing. When RFTS=0, output
clock timing is selected. When RFTS=1, input clock timing is selected. If RFTS is set for input clock timing and an
output clock pin is used, or If RFTS is set for output clock timing and an input clock pin is used, then the setup, hold
and delay timings, as specified in Section
other modes in which there is no input clock pin available for external timing since the clock source is derived
internally from the RX LIU or the CLAD.
X
X
1
1
1
0
0
0
0
0
0
0
0
0
10-5.
not LLB, DLB or PLB (00X)
PLB (011) or DLB (100) or
PLB (011) or DLB (100)
DLB&LLB (110)
not PLB (011)
not PLB (011)
LBM[2:0]
ALB(001)
PLB (011)
PLB (011)
LBM[2:0]
LLB (010)
XXX
XXX
XXX
XXX
XXX
18.1
X
X
X
X
X
X
0
1
0
1
0
1
0
1
will not be valid. There are some combinations of RFTS=1 and
X
X
X
X
X
X
X
X
X
X
X
X
0
1
58
Valid Timing to These Clock Pins
RLCLKn
No valid timing to any clock pin
0
0
0
1
1
0
1
1
0
0
1
1
Valid Timing to These Clock Pins
TCLKOn, TLCLKn, RCLKOn
RLCLKn
No valid timing to any input clock pin
TCLKOn, TLCLKn, RCLKOn
TCLKOn, TLCLKn, RCLKOn
TCLKOn, RCLKOn
TCLKOn
TCLKOn, TLCLKn
No valid timing to any input clock pin
TCLKIn
RLCLKn
No valid timing to any input clock pin