DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 60

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

10.2.5 Gapped Clocks
The transmit and receive output clocks can be gapped in certain configurations. See
for the configuration settings. The gapped clocks are active during DS3 or E3 framed payload bits overhead bits
depending on which mode the device is configured for.
In the internal DS3 or E3 frame modes, the transmit gapped clock is created by the logical OR of the TCLKOn and
TDENn signals creating a positive or negative clock edge for each payload bit, the receive gapped clock is created
by the logical OR of the RCLKOn and RDENn signals.
When the output clock is disabled, the gapped output signal is high during clock periods if the pin is not inverted,
otherwise it will be low.
The gapped clocks are very useful when the data being clocked does not need to be aligned with any frame
structure. The data is simply clocked one bit at a time as a continuous data stream.
10.3 Reset and Power-Down
The device can be reset at a global level via the GL.CR1.RST bit or the RST pin and at the port level via the
PORT.CR1.RST bit and each port can be explicitly powered down via the PORT.CR1.PD bit. The JTAG logic is
reset using the power on reset signal from one of the LIUs as well as from the JTRST pin.
Figure 10-4. Example IO Pin Clock Muxing
TSER
TCLKI
RLCLK
CLAD CLOCKS
STS-1 CLK
RX LIU CLK
DS3 CLK
E3 CLK
PIN INVERT
PIN INVERT
PIN INVERT
DELAY
TFTS
0
1
CLOCK TREE
CLOCK TREE
CLOCK TREE
INTERNAL
INTERNAL
INTERNAL
SIGNAL
SIGNAL
SIGNAL
D
SET
CLR
Q
Q
60
D
D
D
D
SET
CLR
SET
CLR
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
Q
Q
INTERNAL
DELAY
SIGNAL
DELAY
DELAY
TFTS
TLTS
RFTS
0
1
0
1
0
1
D
D
D
SET
CLR
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
Table 10-22
RCLKO
TCLKO
TLCLK
TDEN
RSER
TPOS
and
Table 10-24