SC16C850SVIBS,157 NXP Semiconductors, SC16C850SVIBS,157 Datasheet - Page 10

• Manufacturer Part Number: SC16C850SVIBS,157
• Description: IC UART SGL 1.8V W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS,157

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286785157; SC16C850SVIBS; SC16C850SVIBS

NXP Semiconductors
SC16C850SV
Product data sheet
6.7 Special character detect
6.8 Interrupt priority and time-out interrupts
In the event that the receive buffer is overfilling, the SC16C850SV automatically sends an
Xoff character (when enabled) via the serial TX output to the remote UART. The
SC16C850SV sends the Xoff1/Xoff2 characters as soon as the number of received data in
the receive FIFO passes the programmed trigger level. To clear this condition, the
SC16C850SV will transmit the programmed Xon1/Xon2 characters as soon as the
number of characters in the receive FIFO drops below the programmed trigger level.
A special character detect feature is provided to detect an 8-bit character when EFR[5] is
set. When an 8-bit character is detected, it will be placed on the user-accessible data
stack along with normal incoming RX data. This condition is selected in conjunction with
EFR[3:0] (see
this special mode by setting EFR[3:0] to all zeroes.
The SC16C850SV compares each incoming receive character with Xoff2 data. If a match
occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although
Xon1, Xon2, Xoff1, Xoff2 with eight bits of character information, the actual number of bits
is dependent on the programmed word length. Line Control Register bits LCR[1:0] define
the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[1:0] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the Xon1, Xon2, Xoff1, Xoff2 registers corresponds with the
LSB bit for the received character.
The interrupts are enabled by IER[7:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C850SV
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR indicates the current singular highest priority interrupt
only. A condition can exist where a higher priority interrupt masks the lower priority
interrupt(s) (see
priority interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
Receive Data Ready and Receive Time Out have the same interrupt priority (when
enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver
issues an interrupt after the number of characters have reached the programmed trigger
level. In this case, the SC16C850SV FIFO may hold more characters than the
programmed trigger level. Following the removal of a data byte, the user should re-check
LSR[0] to see if there are any additional characters. A Receive Time Out will not occur if
the receive FIFO is empty. The time-out counter is reset at the center of each stop bit
received or each time the Receive Holding Register (RHR) is read. The actual time-out
value is 4 character time, including data information length, start bit, parity bit, and the size
of stop bit, that is, 1, 1.5, or 2 bit times.
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table
All information provided in this document is subject to legal disclaimers.
Table
24). Note that software flow control should be turned off when using
12). Only after servicing the higher pending interrupt will the lower
Rev. 2 — 22 March 2011
Table 7 “SC16C850SV internal registers”
SC16C850SV
© NXP B.V. 2011. All rights reserved.
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