SC16C850SVIBS,157 NXP Semiconductors, SC16C850SVIBS,157 Datasheet - Page 24

• Manufacturer Part Number: SC16C850SVIBS,157
• Description: IC UART SGL 1.8V W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS,157

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286785157; SC16C850SVIBS; SC16C850SVIBS

NXP Semiconductors
SC16C850SV
Product data sheet
7.5 Line Control Register (LCR)
Table 13.
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 14.
Table 15.
Table 16.
Bit
0
Bit
7
6
5:3
1:0
LCR[5]
X
X
0
0
1
LCR[2]
1
2
0
1
LCR[7]
LCR[6]
LCR[5:3]
LCR[1:0]
Symbol
LCR[2]
Symbol
ISR[0]
LCR[4]
X
0
1
0
1
Interrupt Status Register bits description
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
transmitted (the TX output is forced to a logic 0 state). This condition exists
until disabled by setting LCR[6] to a logic 0.
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
or received (see
Set break. When enabled, the Break control bit causes a break condition to be
Programs the parity conditions (see
Word length bits 1, 0. These two bits specify the word length to be transmitted
LCR[3]
0
1
1
1
1
INT status.
Description
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Rev. 2 — 22 March 2011
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Stop bit length (bit times)
1
2
1
1
Table
⁄
2
17).
Table
…continued
Table
16).
15).
SC16C850SV
© NXP B.V. 2011. All rights reserved.
24 of 48