SC16C850SVIBS,157 NXP Semiconductors, SC16C850SVIBS,157 Datasheet - Page 7

• Manufacturer Part Number: SC16C850SVIBS,157
• Description: IC UART SGL 1.8V W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS,157

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286785157; SC16C850SVIBS; SC16C850SVIBS

NXP Semiconductors
SC16C850SV
Product data sheet
6.2 Extended mode (128-byte FIFO)
6.3 Internal registers
The device is in the extended mode when any of these four registers contains any value
other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.
The SC16C850SV provides a set of 25 internal registers for monitoring and controlling the
functions of the UART. These registers are shown in
Table 4.
[1]
A3
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Second special register set (TXLVLCNT/RXLVLCNT)
0
1
Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2)
0
1
1
1
1
First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)
0
1
1
1
Second extra feature register set (CLKPRES, SAMPR, RS485TIME, AFCR2, AFCR1)
0
0
1
1
1
These registers are accessible only when LCR[7] is a logic 0.
A2
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
1
1
1
0
1
1
Internal registers decoding
A1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Read mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Transmit FIFO Level Count
Receive FIFO Level Count
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Flow Control Count High
Flow Control Count Low
Clock Prescaler
Sampling Rate
RS-485 turn-around Timer
Advanced Feature Control Register 2
Advanced Feature Control Register 1
Rev. 2 — 22 March 2011
[2]
[3]
[4]
Table
Write mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Extra Feature Control Register (EFCR)
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
n/a
n/a
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Flow Control Count High
Flow Control Count Low
Clock Prescaler
Sampling Rate
RS-485 turn-around Timer
Advanced Feature Control Register 2
Advanced Feature Control Register 1
4.
SC16C850SV
[1]
© NXP B.V. 2011. All rights reserved.
[5]
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