SC16C850SVIBS,157 NXP Semiconductors, SC16C850SVIBS,157 Datasheet - Page 18

• Manufacturer Part Number: SC16C850SVIBS,157
• Description: IC UART SGL 1.8V W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS,157

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286785157; SC16C850SVIBS; SC16C850SVIBS

Table 7.
A3 A2 A1 Register
General register set
0
0
0
0
0
0
1
1
1
1
1
Special register set
0
0
Second special register set
0
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
SC16C850SV internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
EFCR
MSR
SPR
DLL
DLM
TXLVLCNT
RXLVLCNT
[4]
[2]
[5]
Default
XX
XX
00
00
01
00
00
60
00
X0
FF
XX
XX
00
00
[1]
Bit 7
bit 7
bit 7
CTS
interrupt
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
clock
select
FIFO data
error
reserved
CD
bit 7
bit 7
bit 15
bit 7
bit 7
[3]
[3]
Bit 6
bit 6
bit 6
RTS
interrupt
RCVR
trigger
(LSB)
FIFOs
enabled
set break
IrDA
enable
THR and
TSR empty
reserved
RI
bit 6
bit 6
bit 14
bit 6
bit 6
[3]
Bit 5
bit 5
bit 5
Xoff
interrupt
TX trigger
(MSB)
INT priority
bit 4
set parity
INT type
THR empty break
reserved
DSR
bit 5
bit 5
bit 13
bit 5
bit 5
[3]
[3]
Bit 4
bit 4
bit 4
Sleep
mode
TX trigger
(LSB)
INT priority
bit 3
even parity
loopback
interrupt
reserved
CTS
bit 4
bit 4
bit 12
bit 4
bit 4
[3]
[3]
reserved
Bit 3
bit 3
bit 3
modem
status
interrupt
reserved
INT priority
bit 2
parity
enable
OP2
framing
error
CD
bit 3
bit 3
bit 11
bit 3
bit 3
Bit 2
bit 2
bit 2
receive line
status
interrupt
XMIT FIFO
reset
INT priority
bit 1
stop bits
OP1
parity error
Enable extra
feature bit-1
RI
bit 2
bit 2
bit 10
bit 2
bit 2
Bit 1
bit 1
bit 1
transmit
holding
register
interrupt
RCVR FIFO
reset
INT priority
bit 0
word length
bit 1
RTS
overrun error receive data
Enable extra
feature bit-0
DSR
bit 1
bit 1
bit 9
bit 1
bit 1
Bit 0
bit 0
bit 0
receive
holding
register
FIFOs
enable
INT status
word length
bit 0
DTR
ready
Enable
TXLVLCNT/
RXLVLCNT
CTS
bit 0
bit 0
bit 8
bit 0
bit 0
R/W
R
W
R/W
W
R
R/W
R/W
R
W
R
R/W
R/W
R/W
R
R