SC16C652BIBS,157 NXP Semiconductors, SC16C652BIBS,157 Datasheet - Page 19

• Manufacturer Part Number: SC16C652BIBS,157
• Description: IC UART DUAL W/FIFO 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C652BIBS,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-2046; 935276387157; SC16C652BIBS

Philips Semiconductors
SC16C652B_4
Product data sheet
Table 11:
Table 12:
Table 13:
Bit
3
(cont.)
2
1
0
FCR[7]
0
0
1
1
FCR[5]
0
0
1
1
Symbol
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
RCVR trigger levels
TX FIFO trigger levels
FCR[6]
0
1
0
1
FCR[4]
0
1
0
1
Description
Transmit operation in mode ‘1’: When the SC16C652B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the
transmit FIFO is completely full. It will be a logic 0 when the trigger level has
been reached.
Receive operation in mode ‘1’: When the SC16C652B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in the
FIFO.
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
Rev. 04 — 1 September 2005
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to, or they will not be programmed.
RX FIFO trigger level (bytes)
8
16
24
28
TX FIFO trigger level (bytes)
16
8
24
30
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
…continued
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC16C652B
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