SC16C652BIBS,157 NXP Semiconductors, SC16C652BIBS,157 Datasheet - Page 24
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SC16C652BIBS,157
Manufacturer Part Number
SC16C652BIBS,157
Description
IC UART DUAL W/FIFO 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C652BIB48128.pdf
(43 pages)
Specifications of SC16C652BIBS,157
Features
2 Channels
Number Of Channels
2, DUART
Fifo's
32 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
32
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-2046
935276387157
SC16C652BIBS
935276387157
SC16C652BIBS
Philips Semiconductors
SC16C652B_4
Product data sheet
7.8 Modem Status Register (MSR)
7.9 Scratchpad Register (SPR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C652B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
Table 22:
[1]
The SC16C652B provides a temporary data register to store 8 bits of user information.
Bit
7
6
5
4
3
2
1
0
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
Description
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the loop-back mode produces the state of MCR[3] (OP2).
RI. During normal operation, this bit is the complement of the RI input.
Reading this bit in the loop-back mode produces the state of MCR[2] (OP1).
DSR. During normal operation, this bit is the complement of the DSR input.
During the loop-back mode, this bit is equivalent to MCR[0] (DTR).
CTS. During normal operation, this bit is the complement of the CTS input.
During the loop-back mode, this bit is equivalent to MCR[1] (RTS).
Rev. 04 — 1 September 2005
CD
RI
DSR
CTS
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C652B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C652B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C652B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C652B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
[1]
[1]
[1]
[1]
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC16C652B
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