SC16C852SVIET,115 NXP Semiconductors, SC16C852SVIET,115 Datasheet - Page 34

• Manufacturer Part Number: SC16C852SVIET,115
• Description: IC UART DL 1.8V W/FIFO 36-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852SVIET,115

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286451115; SC16C852SVIET-G; SC16C852SVIET-G

NXP Semiconductors
SC16C852SV_1
Product data sheet
7.20 Sampling Rate (SAMPR)
7.21 RS-485 turn-around time delay (RS485TIME)
7.22 Advanced Feature Control Register 1 (AFCR1)
Bit 1 and bit 0 of this register program the device’s sampling rate.
Table 30.
The value in this register controls the turn-around time of the external line transceiver in
bit time. In automatic 9-bit mode, the RTSA/RTSB or DTRA/DTRB pin is used to control
the direction of the line driver, after the last bit of data has been shifted out of the transmit
shift register the UART will count down the value in this register. When the count value
reaches zero, the UART will assert the RTSA/RTSB or DTRA/DTRB pin (logic 0) to turn
the external RS-485 transceiver around for receiving.
Table 31.
Table 32.
Bit
7:2
1:0
Bit
7:0
Bit
7
6:5
4
3
2
Symbol
RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value
Symbol
AFCR1[7]
AFCR1[6:5]
AFCR1[4]
AFCR1[3]
AFCR1[2]
Symbol
SAMPR[7:2]
SAMPR[1:0]
Sampling rate
RS-485 programmable turn-around time register
Advanced Feature Control Register 1 bits description
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 01 — 23 September 2008
Description
Concurrent write. When this bit is set the host can write concurrently to the
same register of all channels.
reserved
Sleep RXlow. Program RX input to be edge-sensitive or level-sensitive.
reserved
RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
0 = normal operation
1 = concurrent write operation
0 = RX input is level sensitive. If RXA/RXB pin is LOW, the UART will not
go to sleep. Once the UART is in Sleep mode, it will wake up if RXA/RXB
pin goes LOW.
1 = RX input is edge sensitive. UART will go to sleep even if RXA/RXB
pin is LOW, and will wake up when RXA/RXB pin toggles.
0 = RTS and CTS signals are used for hardware flow control
1 = DTR and DSR signals are used for hardware flow control. RTS and
CTS retain their functionality.
Description
represents the bit time at the programmed baud rate.
Description
reserved
sampling rate
00 = 16
01 = 8
10 = 4
11 = reserved
SC16C852SV
© NXP B.V. 2008. All rights reserved.
34 of 48