SC16C2552BIA44,512 NXP Semiconductors, SC16C2552BIA44,512 Datasheet
SC16C2552BIA44,512
Specifications of SC16C2552BIA44,512
SC16C2552BIA44
SC16C2552BIA44
Related parts for SC16C2552BIA44,512
SC16C2552BIA44,512 Summary of contents
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SC16C2552B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 03 — 12 February 2009 1. General description The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name SC16C2552BIA44 PLCC44 4. Block diagram SC16C2552B DATA BUS IOR IOW CONTROL RESET REGISTER CS SELECT CHSEL INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C2552B SC16C2552B_3 Product data sheet ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Pin description Symbol Pin Type Description Register select are used during read and write operations to select the UART register to read from or write to CDA 42 I Carrier detect A, B (active LOW). These inputs are associated with individual UART channels A through B ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Type Description D0 2 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU I/O DSRA 41 I Data Set Ready A, B (active LOW). These inputs are associated with individual UART channels A through B ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Type Description RTSA 36 O Request to Send A, B (active LOW). These outputs are associated with individual UART channels A through B. A logic 0 on the RTSn pin indicates the transmitter is ready to RTSB 23 O transmit data. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating that the transmitter is ready to transmit data ...
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... NXP Semiconductors 6. Functional description The SC16C2552B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character ...
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... NXP Semiconductors 6.2 Internal registers The SC16C2552B provides two sets of internal registers (A and B) consisting of 13 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control ...
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... NXP Semiconductors When two interrupt conditions have the same priority important to service these interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C2552B FIFO may hold more characters than the programmed trigger level ...
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... NXP Semiconductors Table 5. Output baud rate 50 75 150 300 600 1200 2400 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k 6.6 DMA operation The SC16C2552B FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an empty location(s) ...
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... NXP Semiconductors made available at the user data interface D0 to D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status Register bits 7:4 ...
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... NXP Semiconductors 7. Register descriptions Table 6 assigned bit functions are further defined in Table 6. SC16C2552B internal registers Register Default [2] General register set RHR THR IER FCR ISR LCR MCR LSR MSR SPR FF [3] Special register set DLL DLM AFR 00 [1] The value shown represents the register’s initialized hexadecimal value not applicable. ...
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... NXP Semiconductors 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0) to the TSR and UART via the THR, providing that the THR is empty. The THR empty fl ...
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... NXP Semiconductors 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive FIFO has reached the programmed trigger level ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit Set and enable the interrupt for each single transmit or receive operation and is similar to the 16C450 mode ...
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... NXP Semiconductors Table 8. Bit 3 (continued Table 9. FCR[ SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a logic 1 when the transmit FIFO is completely full ...
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... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C2552B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits and the parity are selected by writing the appropriate bits in this register. Table 12. Bit 7 6 5:3 2 1:0 Table 13 ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 16. Bit 7 SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Modem Control Register bits description Symbol ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2552B and the CPU. Table 17. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem or other peripheral device to which the SC16C2552B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...
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... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C2552B provides a temporary data register to store 8 bits of user information. 7.10 Alternate Function Register (AFR) This is a read/write register used to select specific modes of MF operation and to allow both UART register’s sets to be written concurrently. ...
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... NXP Semiconductors 7.11 SC16C2552B external reset condition Table 21. Register IER ISR LCR MCR LSR MSR FCR AFR Table 22. Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB INTA, INTB TXRDYA, TXRDYB 8. Limiting values Table 23. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 24. Static characteristics +85 C; tolerance of V amb Symbol Parameter V clock LOW-level input IL(clk) voltage V clock HIGH-level input IH(clk) voltage V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage OL V HIGH-level output voltage LOW-level input leakage ...
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... NXP Semiconductors 10. Dynamic characteristics Table 25. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t pulse width HIGH WH t pulse width LOW WL f frequency on pin XTAL1 XTAL1 t address set-up time 6s t address hold time 6h t IOR delay from chip select 7d t IOR strobe width ...
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... NXP Semiconductors Table 25. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t delay from start to reset 28d TXRDY t RESET pulse width RESET N baud rate divisor [1] Applies to external clock, crystal oscillator max 24 MHz. 1 -------------- - [2] Maximum frequency = t w clk [3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches. ...
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... NXP Semiconductors CHSEL IOR Fig 6. General read timing IOW RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB INTA, INTB IOR RIA, RIB Fig 7. Modem input/output timing SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors external clock -------------- - XTAL1 t w clk Fig 8. External clock timing RXA, RXB INTA, INTB IOR Fig 9. Receive timing SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs w(clk) start bit data bits ( data bits ...
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... NXP Semiconductors RXA, RXB RXRDYA, RXRDYB IOR Fig 10. Receive ready timing in non-FIFO mode RXA, RXB RXRDYA, RXRDYB IOR Fig 11. Receive ready timing in FIFO mode SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit ...
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... NXP Semiconductors TXA, TXB INTA, INTB active IOW Fig 12. Transmit timing TXA, TXB active IOW byte #1 TXRDYA, TXRDYB Fig 13. Transmit ready timing in non-FIFO mode SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit ...
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... NXP Semiconductors TXA, TXB IOW active byte #16 TXRDYA, TXRDYB Fig 14. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C2552B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits ( data bits 6 data bits ...
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... NXP Semiconductors 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 28. Acronym CPU DLL DLM DMA FIFO ISDN LSB MSB UART SC16C2552B_3 Product data sheet ...
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... Release date SC16C2552B_3 20090212 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 – added (new) 5 – added • ...
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... NXP Semiconductors Table 29. Revision history …continued Document ID Release date • Modifications: Section 10.1 “Timing (continued) – Figure (channel) “A” and/or “B” to signal names – Figure 8 “External clock respectively – Figure 8 “External clock – Figure from “DATA BITS (5-8)” to “data bits (0 to 7)” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 6 6.2 Internal registers 6.3 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.4 Time-out interrupts . . . . . . . . . . . . . . . . . . . . . . 7 6.5 Programmable baud rate generator . . . . . . . . . 8 6 ...