IS82C50A-5Z Intersil, IS82C50A-5Z Datasheet - Page 12

• Manufacturer Part Number: IS82C50A-5Z
• Description: IC PERIPH UART/BRG 10MHZ 44-PLCC
• Manufacturer: Intersil

Specifications of IS82C50A-5Z

• Features: Single Chip UART/BRG
• Number Of Channels: 1, UART
• Protocol: RS232C
• Voltage - Supply: 4.5 V ~ 5.5 V
• With Parallel Port: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE: X = Not Defined, May Be 0 or 1
data in the RBR before complete reception of the next
character result in the loss of the data in the Receiver
Register. The OE flag in the LSR register indicates the
overrun condition.
RBR Bits 0 thru 7
TRANSMITTER HOLDING REGISTER (THR)
The Transmitter Holding Register (THR) holds parallel data
from the data bus (D0-D7) until the Transmitter Shift Register
is empty and ready to accept a new character for
transmission. The transmitter and receiver word length and
number of stop bits are the same. If the character is less
than eight bits, unused bits at the microprocessor data bus
are ignored by the transmitter.
Data Bit 0 (THR(0)) is the first serial data bit transmitted. The
THRE flag (LSR(5)) reflect the status of the THR. The TEMT
flag (LSR(6)) indicates if both the THR and TSR are empty.
THR Bits 0 thru 7
SCRATCHPAD REGISTER (SCR)
This 8-bit Read/Write register has no effect on the 82C50A.
It is intended as a scratchpad register to be used by the
programmer to hold data temporarily.
BIT 2
X
1
1
0
0
INTERRUPT IDENTIFICATION
BIT 1
X
1
0
1
0
RBR (0)
RBR (1)
RBR (2)
RBR (3)
RBR (4)
RBR (5)
RBR (6)
RBR (7)
THR (0)
THR (1)
THR (2)
THR (3)
THR (4)
THR (5)
THR (6)
THR (7)
BIT 0
1
0
0
0
0
12
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
PRIORITY
Second
LEVEL
Fourth
Third
First
TABLE 2. INTERRUPT IDENTIFICATION REGISTER
Received Data Available
Receiver Line Status
INTERRUPT FLAG
Modem Status
THRE
None
82C50A
SCR Bits 0 thru 7
Interrupt Structure
INTERRUPT IDENTIFICATION REGISTER (IIR)
The 82C50A has interrupt capability for interfacing to current
microprocessors. In order to minimize software overhead
during data character transfers, the 82C50A prioritizes
interrupts into four levels. The four levels of interrupt
conditions are as follows:
1. Receiver Line Status (Priority 1)
2. Received Data Ready (Priority 2)
3. Transmitter Holding Register Empty (Priority 3)
4. Modem Status (Priority 4).
Information indicating that a prioritized interrupt is pending
and the type of interrupt is stored in the Interrupt
Identification Register (IIR). When addressed during chip
select time, the lIR indicates the highest priority interrupt
pending. No other interrupts are acknowledged until the
interrupt is serviced by the CPU. The contents of the lIR are
indicated in Table 2 and are described below.
IIR(0): IIR(0) can be used in either a hardwired prioritized or
polled environment to indicate whether an interrupt is
pending. When IIR(0) is low, an interrupt is pending, and the
lIR contents may be used as a pointer to the appropriate
interrupt service routine. When lIR(0) is high, no interrupt is
pending.
IlR(1) and IIR(2): llR(1) and IlR(2) are used to identify the
highest priority interrupt pending as indicated in Table 2.
lIR(3) - IIR(7): These five bits of the lIR are logic 0.
INTERRUPT SET AND RESET FUNCTIONS
Receiver Data Available
INTERRUPT SOURCE
CTS, DSR, RI, DCD
OE, PE, FE, or BI
SCR (0)
SCR (1)
SCR (2)
SCR (3)
SOR (4)
SCR (5)
SOR (6)
SCR (7)
THRE
None
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Interrupt Source or THR Write
IIR Read if THRE is the
RESET CONTROL
INTERRUPT
MSR Read
RBR Read
LSR Read
August 24, 2006
FN2958.5