IS82C50A-5Z Intersil, IS82C50A-5Z Datasheet - Page 13

• Manufacturer Part Number: IS82C50A-5Z
• Description: IC PERIPH UART/BRG 10MHZ 44-PLCC
• Manufacturer: Intersil

Specifications of IS82C50A-5Z

• Features: Single Chip UART/BRG
• Number Of Channels: 1, UART
• Protocol: RS232C
• Voltage - Supply: 4.5 V ~ 5.5 V
• With Parallel Port: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERRUPT ENABLE REGISTER (IER)
The Interrupt Enable Register (IER) is a Write register used
to independently enable the four 82C50A interrupts which
activate the interrupt (lNTRPT) output. All interrupts are
disabled by resetting IER(0) - IER(3) of the Interrupt Enable
Register. Interrupts are enabled by setting the appropriate
bits of the IER high. Disabling the interrupt system inhibits
the Interrupt Identification Register and the active (high)
INTRPT output. All other system functions operate in their
normal manner, including the setting of the Line Status and
Modem Status Registers. The contents of the Interrupt
Enable Register are indicated in Table 3 and are described
below.
IER(0): When programmed high (IER(0) = Logic 1), IER(0)
enables Received Data Available interrupt.
IER(1): When programmed high (IER(1) = Logic 1), IER(1)
enables the Transmitter Holding Register Empty interrupt.
IER(2): When Programmed high (IER(2) = Logic 1), IER(2)
enables the Receiver Line Status interrupt.
†LSB, Data Bit 0 is the first bit transmitted or received.
MNEMONIC
(Read Only)
(Read Only)
(Write Only)
REGISTER
MCR
MSR
RBR
DLM
SCR
THR
LCR
LSR
DLL
IER
IIR
Data Bit 7
Data Bit 7
(DLAB)
Access
Divisor
Carrier
(MSB)
(DCD)
Detect
Bit 15
BIT 7
Latch
Data
Bit 7
Bit 7
Bit
0
0
0
0
13
Transmitter
Data Bit 6
Data Bit 6
Set Break
Indicator
(TEMT)
Empty
Bit 14
BIT 6
Ring
Bit 6
Bit 6
(RI)
0
0
0
TABLE 3. 82C50A ACCESSIBLE REGISTER SUMMARY
(NOTE: See Table 1 for how to access these registers.)
Transmitter
Stick Parity
Data Bit 5
Data Bit 5
Register
(THRE)
Holding
Empty
(DSR)
Ready
Bit 13
BIT 5
Data
Bit 5
Bit 5
Set
0
0
0
82C50A
Even Parity
REGISTER BIT NUMBER
Data Bit 4
Data Bit 4
Interrupt
(EPS)
Select
(CTS)
Bit 12
Break
BIT 4
Clear
Loop
Send
Bit 4
Bit 4
(BI)
to
0
0
IER(3): When programmed high (IER(3) = Logic 1), IER(3)
enables the Modem Status interrupt.
IER(4) - IER(7): These four bits of the IER are logic 0.
DDCD (MSR BIT 3)
DDSR (MSR BIT 1)
DCTS (MSR BIT 0)
ERBFI (IER BIT 0)
THRE (LSR BIT 5)
EDSSI (IER BIT 3)
ETBEI (IER BIT 1)
TERI (MSR BIT 2)
ELSI (IER BIT 2)
FIGURE 1. 82C50A INTERRUPT CONTROL STRUCTURE
DR (LSR BIT 0)
OE (LSR BIT 1)
PE (LSR BIT 2)
FE (LSR BIT 3)
BI (LSR BIT 4)
Data Bit 3
Data Bit 3
Interrupt
(EDSSI)
Framing
(DDCD)
Modem
Enable
Enable
Carrier
Detect
Status
(PEN)
Parity
BIT 3
Bit 11
Out 2
Error
Delta
Data
Bit 3
(FE)
Bit 3
0
Interrupt ID
Data Bit 2
Data Bit 2
Receiver
Interrupt
Indicator
Number
of Stop
Trailing
Enable
(ELSI)
(TERI)
Status
Bit (1)
Bit 10
(STB)
Parity
BIT 2
Out 1
Edge
Error
Bit 2
(PE)
Ring
Bit 2
Line
Bits
Transmitter
Interrupt ID
Data Bit 1
Data Bit 1
(WLSB1)
Register
Interrupt
Request
Overrun
(ETBEI)
to Send
(DDSR)
Holding
Enable
Length
Empty
Ready
Select
Bit (0)
(RTS)
BIT 1
Word
Delta
(OE)
Error
Data
Bit 1
Bit 9
Bit 1
Bit 1
Set
Data Bit 0
Data Bit 0
Received
Available
(WLSB0)
Terminal
(ERBFI)
Interrupt
Interrupt
Pending
(DCTS)
(LSB)†
Enable
Length
Ready
Ready
Select
(DTR)
“0” 1F
BIT 0
Word
Delta
Clear
Send
(DR)
Bit 0
Bit 8
Data
Bit 0
Data
Data
Bit 0
August 24, 2006
to
INTRPT
PIN 30
FN2958.5