SC16C654IA68,529 NXP Semiconductors, SC16C654IA68,529 Datasheet - Page 29
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SC16C654IA68,529
Manufacturer Part Number
SC16C654IA68,529
Description
IC UART QUAD W/FIFO 68-PLCC
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C654DIB64151.pdf
(52 pages)
Specifications of SC16C654IA68,529
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3282-5
935270051529
SC16C654IA68-S
935270051529
SC16C654IA68-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654IA68,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11617
Product data
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C654/654D and
the CPU.
Table 20:
Bit
7
6
5
4
3
2
1
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
LSR[1]
Line Status Register bits description
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Description
FIFO data error.
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is
set to a logic 1 whenever the transmit holding register and the transmit
shift register are both empty. It is reset to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’
whenever the transmit FIFO and transmit shift register are both empty.
THR empty. This bit is the Transmit Holding Register Empty indicator.
This bit indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to
CPU when the THR interrupt enable is set. The THR bit is set to a logic 1
when a character is transferred from the transmit holding register into the
transmitter shift register. The bit is reset to a logic 0 concurrently with the
loading of the transmitter holding register by the CPU. In the FIFO mode,
this bit is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
Break interrupt.
Framing error.
Parity error.
Overrun error.
Rev. 04 — 19 June 2003
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break indication is in
the current FIFO data. This bit is cleared when LSR register is read.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0 for
one character frame time). In the FIFO mode, only one break character
is loaded into the FIFO.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at
the top of the FIFO.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error. The receive character does not have correct
parity information and is suspect. In the FIFO mode, this error is
associated with the character at the top of the FIFO.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the receive
shift register. This happens when additional data arrives while the FIFO
is full. In this case, the previous data in the shift register is overwritten.
Note that under this condition, the data byte in the receive shift register
is not transferred into the FIFO, therefore the data in the FIFO is not
corrupted by the error.
SC16C654/654D
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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