SC16C754IA68,529 NXP Semiconductors, SC16C754IA68,529 Datasheet - Page 24
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SC16C754IA68,529
Manufacturer Part Number
SC16C754IA68,529
Description
IC UART QUAD W/FIFO 68-PLCC
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C754IA68529.pdf
(49 pages)
Specifications of SC16C754IA68,529
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3291-5
935270056529
SC16C754IA68-S
935270056529
SC16C754IA68-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C754IA68,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11618
Product data
7.4 Line control register (LCR)
This register controls the data communication format. The word length, number of
stop bits, and parity type are selected by writing the appropriate bits to the LCR.
Table 12
Table 12:
Bit
7
6
5
4
3
2
1-0
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1-0]
shows the line control register bit settings.
Line Control Register bits description
Rev. 04 — 19 June 2003
Description
Divisor latch enable.
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
Parity type select.
Parity enable.
Number of Stop bits. Specifies the number of stop bits.
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition.
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
Logic 0 = ODD Parity is generated (if LCR[3] = 1).
Logic 1 = EVEN Parity is generated (if LCR[3] = 1).
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during transmission and the
receiver checks for received parity.
0 = 1 stop bit (word length = 5, 6, 7, 8)
1 = 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
00 - 5 bits
01 - 6 bits
10 - 7 bits
11 - 8 bits
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
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