SC16C754IA68,529 NXP Semiconductors, SC16C754IA68,529 Datasheet - Page 28
![IC UART QUAD W/FIFO 68-PLCC](/photos/6/98/69865/68-plcc_sot188-3_pkg_sml.jpg)
SC16C754IA68,529
Manufacturer Part Number
SC16C754IA68,529
Description
IC UART QUAD W/FIFO 68-PLCC
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C754IA68529.pdf
(49 pages)
Specifications of SC16C754IA68,529
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3291-5
935270056529
SC16C754IA68-S
935270056529
SC16C754IA68-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C754IA68,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11618
Product data
7.9 Interrupt identification register (IIR)
Table 16:
[1]
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner.
Table 17:
The interrupt priority list is shown in
Bit
4
3
2
1
0
Bit
7-6
5
4
3-1
0
IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will
not cause a new interrupt if the THR is below the threshold.
Symbol
IER[4]
IER[3]
IER[2]
IER[1]
IER[0]
Symbol
IIR[7:6]
IIR[5]
IIR[4]
IIR[3:1]
IIR[0]
Interrupt Enable Register bits description
Interrupt Identification Register bits description
[1]
Description
Sleep mode.
Modem Status Interrupt.
Receive Line Status interrupt.
Transmit Holding Register interrupt.
Receive Holding Register interrupt.
Description
Mirror the contents of FCR[0].
RTS/CTS LOW-to-HIGH change of state.
1 = Xoff/Special character has been detected.
3-bit encoded interrupt. See
Interrupt status.
Rev. 04 — 19 June 2003
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
Logic 0 = Disable the THR interrupt (normal default condition).
Logic 1 = Enable the THR interrupt.
Logic 0 = Disable the RHR interrupt (normal default condition).
Logic 1 = Enable the RHR interrupt.
Logic 0 = An interrupt is pending.
Logic 1 = No interrupt is pending.
Table 17
shows interrupt identification register bit settings.
Table
18.
Table
18.
Section 6.7 “Sleep mode”
…continued
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
for details.
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